EFM32WG Datasheet, PDF (809/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
11
SEGD3H
0
R
SEGD3H Register Busy
Set when the value written to SEGD3H is being synchronized.
10
SEGD2H
0
R
SEGD2H Register Busy
Set when the value written to SEGD2H is being synchronized.
9
SEGD1H
0
R
SEGD1H Register Busy
Set when the value written to SEGD1H is being synchronized.
8
SEGD0H
0
R
SEGD0H Register Busy
Set when the value written to SEGD0H is being synchronized.
7
SEGD3L
0
R
SEGD3L Register Busy
Set when the value written to SEGD3L is being synchronized.
6
SEGD2L
0
R
SEGD2L Register Busy
Set when the value written to SEGD2L is being synchronized.
5
SEGD1L
0
R
SEGD1L Register Busy
Set when the value written to SEGD1L is being synchronized.
4
SEGD0L
0
R
SEGD0L Register Busy
Set when the value written to SEGD0L is being synchronized.
3
AREGB
0
R
AREGB Register Busy
Set when the value written to AREGB is being synchronized.
2
AREGA
0
R
AREGA Register Busy
Set when the value written to AREGA is being synchronized.
1
BACTRL
0
R
BACTRL Register Busy
Set when the value written to BACTRL is being synchronized.
0
CTRL
0
R
CTRL Register Busy
Set when the value written to CTRL is being synchronized.
33.5.22 LCD_SEGD4H - Segment Data High Register 4 (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 21) .
Offset
0x0B4
Reset
Bit Position
Access
Name
Bit
Name
Reset
Access Description
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
7:0
SEGD4H
0x00
RW
COM0 Segment Data High
This register contains segment data for segment lines 32-39 for COM0.
33.5.23 LCD_SEGD5H - Segment Data High Register 5 (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 21) .
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
809
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