EFM32WG Datasheet, PDF (515/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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19.5.15 LEUARTn_IEN - Interrupt Enable Register
Offset
0x038
Reset
Access
Bit Position
Name
Bit
31:11
10
9
8
7
6
5
4
3
2
1
0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
SIGF
0
RW
Signal Frame Interrupt Enable
Enable interrupt on signal frame.
STARTF
0
RW
Start Frame Interrupt Enable
Enable interrupt on start frame.
MPAF
0
RW
Multi-Processor Address Frame Interrupt Enable
Enable interrupt on multi-processor address frame.
FERR
0
RW
Framing Error Interrupt Enable
Enable interrupt on framing error.
PERR
0
RW
Parity Error Interrupt Enable
Enable interrupt on parity error.
TXOF
0
RW
TX Overflow Interrupt Enable
Enable interrupt on TX overflow.
RXUF
0
RW
RX Underflow Interrupt Enable
Enable interrupt on RX underflow.
RXOF
0
RW
RX Overflow Interrupt Enable
Enable interrupt on RX overflow.
RXDATAV
0
RW
RX Data Valid Interrupt Enable
Enable interrupt on RX data.
TXBL
0
RW
TX Buffer Level Interrupt Enable
Enable interrupt on TX buffer level.
TXC
0
RW
TX Complete Interrupt Enable
Enable interrupt on TX complete.
19.5.16 LEUARTn_PULSECTRL - Pulse Control Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 21) .
Offset
0x03C
Reset
Access
Bit Position
Name
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
515
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