EFM32WG Datasheet, PDF (59/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

...the world's most energy friendly microcontrollers
Figure 8.4. Memory scatter-gather example
Init ializat ion:1. Configure prim ary t o enable t he copy A, B, C, and D operat ions: cycle_ct rl = b100, 2^R = 4, N = 16.
2. Write the prim ary source data to m em ory, using the structure shown in the following table.
Dat a for Task A
Dat a for Task B
Dat a for Task C
Dat a for Task D
src_dat a_end_pt r
0 x 0 A0 0 0 0 0 0
0 x 0 B0 0 0 0 0 0
0 x 0 C0 0 0 0 0 0
0x0D000000
dst _dat a_end_pt r
0 x 0 AE0 0 0 0 0
0 x 0 BE0 0 0 0 0
0 x 0 CE0 0 0 0 0
0 x 0 D E0 0 0 0 0
c h a n n e l _c f g
cycle_ct rl = b101, 2^R = 4, N = 3
cycle_ct rl = b101, 2^R = 2, N = 8
cycle_ct rl = b101, 2^R = 8, N = 5
cycle_ct rl = b010, 2^R = 4, N = 4
Unused
0 x XXXXXXXX
0 x XXXXXXXX
0 x XXXXXXXX
0 x XXXXXXXX
Mem ory scatter-gather transaction:
Prim a ry
Alt e r n a t e
Re q u e st
Copy from A in
m em ory, to Alternate
Copy from B in
m em ory, to Alternate
Au t o
request
Au t o
request
Task A
N = 3, 2^R = 4
Au t o
request
Auto request
Auto request
Auto request
Au t o
Copy from C in
request
m em ory, to Alternate
Task B
N = 8, 2^R = 2
Au t o
request
Copy from D in
m em ory, to Alternate
Au t o
request
Task C
N = 5, 2^R = 8
Au t o
request
Task D
N = 4, 2^R = 4
d m a _d on e [ C]
In Figure 8.4 (p. 59) :
Initialization
1. The host processor configures the primary data structure to operate in memory
scatter-gather mode by setting cycle_ctrl to b100. Because a data structure for a
single channel consists of four words then you must set 2^R to 4. In this example,
there are four tasks and therefore N is set to 16.
2. The host processor writes the data structure for tasks A, B, C, and D to the
memory locations that the primary src_data_end_ptr specifies.
3. The host processor enables the channel.
The memory scatter-gather transaction commences when the controller receives a request on
dma_req[ ] or a manual request from the host processor. The transaction continues as follows:
Primary, copy A
Task A
Primary, copy B
Task B
Primary, copy C
1. After receiving a request, the controller performs four DMA transfers. These
transfers write the alternate data structure for task A.
2. The controller generates an auto-request for the channel and then arbitrates.
3. The controller performs task A. After it completes the task, it generates an
auto-request for the channel and then arbitrates.
4. The controller performs four DMA transfers. These transfers write the alternate
data structure for task B.
5. The controller generates an auto-request for the channel and then arbitrates.
6. The controller performs task B. After it completes the task, it generates an
auto-request for the channel and then arbitrates.
7. The controller performs four DMA transfers. These transfers write the alternate
data structure for task C.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
59
www.energymicro.com