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Figure 14.39. EBI TFT Pixel Timing
EBI_DCLK
EBI_AD[ 15:0] Z
DCLKPERIOD
(1, 2, 3, ...)
PIXEL N
Z
TFTSETUP TFTHOLD
(0, 1, 2, ...) (0, 1, 2, ...)
DCLKPERIOD
(1, 2, 3, ...)
PIXEL N+ 1
Z
TFTSETUP TFTHOLD
(0, 1, 2, ...) (0, 1, 2, ...)
When driving the TFT from internal memory, the TFT timing is defined in the EBI_TFTTIMING register
as shown in Figure 14.40 (p. 204) . Before each TFT transaction to the visible part of the display, the
EBI will request new pixel data via an interrupt or DMA request. At the time specified in the TFTSTART
bitfield of the EBI_TFTTIMING register (and when pixel data has been provided), the TFT transaction will
start. For internal Direct Drive the TFT state machine will place the pixel data on the EBI_AD lines during
the TFTWDATA state after which the state machine will pass through the programmable TFTSETUP
and TFTHOLD states.
Figure 14.40. EBI TFT Direct Drive Internal Timing
TFTSTART
(1, 2, 3, ...)
TFTWDATA
(1)
TFTSETUP
(0, 1, 2, ...)
TFTHOLD
(0, 1, 2, ...)
EBI_AD[ 15:0]
Z
DATA[ 15:0]
Z
EBI_DCLK
When the TFT is driven directly from an external memory, the timing definitions for the bank defined in
the BANKSEL bitfield of the EBI_TFTCTRL register and those for the TFT are both used by Direct Drive
to generate transactions satisfying the requirements of both the memory device and the TFT display. The
timing definition for the external memory device should be programmed according to its requirements
independent of the TFT timing. Figure 14.41 (p. 204) shows an example of the Direct Drive engine
accessing an external memory using the multiplexed 16-bit data, 16-bit address (D16A16ALE) mode.
The TFTSETUP and TFTHOLD states are now enclosed within the read transaction states of the chosen
mode. The external device read transaction is started at a time as defined by TFTSTART. The read
strobe on EBI_REn is automatically extended in duration to satisfy the TFT setup and hold requirements
defined in the TFTSETUP and TFTHOLD bitfields.
Figure 14.41. EBI TFT Direct Drive External Timing
TFTSTART ADDRSETUP RDSETUP
(1, 2, 3, ...)
(1, 2, 3, ...)
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
TFTSETUP
(0, 1, 2, ...)
TFTHOLD
(0, 1, 2, ...)
RDHOLD
(0, 1, 2, ...)
EBI_AD[ 15:0]
ADDR[ 16:1]
Z
DATA[ 15:0]
Z
EBI_ALE
EBI_CSn
EBI_REn
EBI_DCLK
The timing parameters related to the horizontal timing are shown in Figure 14.42 (p. 205) . These
parameters are defined as pixel or EBI_DCLK counts. The horizontal porch widths are defined in the
HBPORCH and HFPORCH bitfields of the EBI_TFTHPORCH register. A porch which has its width
parameter programmed to 0 will be skipped. The width and start position of the horizontal synchronization
pulse EBI_HSYNC is programmed via the HSYNC and HSYNCSTART bitfields in the EBI_TFTHPORCH
register.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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