EFM32WG Datasheet, PDF (473/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
When enabled, the output on USn_CS will be activated one baud-period before transmission starts, and deactivated when
transmission ends.
15
CSINV
0
RW
Chip Select Invert
Default value is active low. This affects both the selection of external slaves, as well as the selection of the microcontroller as a slave.
Value
0
1
Description
Chip select is active low
Chip select is active high
14
TXINV
0
RW
Transmitter output Invert
The output from the USART transmitter can optionally be inverted by setting this bit.
Value
0
1
Description
Output from the transmitter is passed unchanged to U(S)n_TX
Output from the transmitter is inverted before it is passed to U(S)n_TX
13
RXINV
0
RW
Receiver Input Invert
Setting this bit will invert the input to the USART receiver.
Value
0
1
Description
Input is passed directly to the receiver
Input is inverted before it is passed to the receiver
12
TXBIL
0
RW
TX Buffer Interrupt Level
Determines the interrupt and status level of the transmit buffer.
Value
0
1
Mode
EMPTY
HALFFULL
Description
TXBL and the TXBL interrupt flag are set when the transmit buffer becomes empty.
TXBL is cleared when the buffer becomes nonempty.
TXBL and TXBLIF are set when the transmit buffer goes from full to half-full or empty.
TXBL is cleared when the buffer becomes full.
11
CSMA
0
RW
Action On Slave-Select In Master Mode
This register determines the action to be performed when slave-select is configured as an input and driven low while in master mode.
Value
0
1
Mode
NOACTION
GOTOSLAVEMODE
Description
No action taken
Go to slave mode
10
MSBF
0
RW
Most Significant Bit First
Decides whether data is sent with the least significant bit first, or the most significant bit first.
Value
0
1
Description
Data is sent with the least significant bit first
Data is sent with the most significant bit first
9
CLKPHA
0
RW
Clock Edge For Setup/Sample
Determines where data is set-up and sampled according to the bus clock when in synchronous mode.
Value
0
1
Mode
SAMPLELEADING
SAMPLETRAILING
Description
Data is sampled on the leading edge and set-up on the trailing edge of the bus clock
in synchronous mode
Data is set-up on the leading edge and sampled on the trailing edge of the bus clock
in synchronous mode
8
CLKPOL
0
RW
Clock Polarity
Determines the clock polarity of the bus clock used in synchronous mode.
Value
0
1
Mode
IDLELOW
IDLEHIGH
Description
The bus clock used in synchronous mode has a low base value
The bus clock used in synchronous mode has a high base value
7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
6:5
OVS
0x0
RW
Oversampling
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
473
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