EFM32WG Datasheet, PDF (714/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

Bit
Name
Reset
0
EN
0
Enable/disable channel 1.
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Access
RW
Description
Channel 1 Enable
29.5.5 DACn_IEN - Interrupt Enable Register
Offset
0x010
Reset
Access
Bit Position
Name
Bit
Name
Reset
Access Description
31:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
5
CH1UF
0
RW
Channel 1 Conversion Data Underflow Interrupt Enable
Enable/disable channel 1 data underflow interrupt.
4
CH0UF
0
RW
Channel 0 Conversion Data Underflow Interrupt Enable
Enable/disable channel 0 data underflow interrupt.
3:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
1
CH1
0
RW
Channel 1 Conversion Complete Interrupt Enable
Enable/disable channel 1 conversion complete interrupt.
0
CH0
0
RW
Channel 0 Conversion Complete Interrupt Enable
Enable/disable channel 0 conversion complete interrupt.
29.5.6 DACn_IF - Interrupt Flag Register
Offset
0x014
Reset
Access
Bit Position
Name
Bit
Name
Reset
Access Description
31:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
5
CH1UF
0
R
Channel 1 Data Underflow Interrupt Flag
Indicates channel 1 data underflow.
4
CH0UF
0
R
Channel 0 Data Underflow Interrupt Flag
Indicates channel 0 data underflow.
3:2
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
1
CH1
0
R
Channel 1 Conversion Complete Interrupt Flag
Indicates channel 1 conversion complete and that new data can be written to the data register.
0
CH0
0
R
Channel 0 Conversion Complete Interrupt Flag
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
714
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