EFM32WG Datasheet, PDF (274/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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1. Initialize and enable channel 2 as explained in Channel Initialization (p. 252) .
2. The host writes an IN request to the Request queue as soon as the channel 2 gets the grant from
the arbiter (round-robin with fairness). In high-bandwidth transfers, the host writes consecutive writes
up to MC times.
3. The host attempts to send an IN token at the beginning of the next (odd) frame.
4. As soon the packet is received and written to the receive FIFO, the host generates a CHHLTD
interrupt.
5. In response to the CHHLTD interrupt, reinitialize the channel for the next transfer.
15.4.3.6.12.2 Handling Interrupts
The channel-specific interrupt service routine for Interrupt IN transactions in DMA mode is as follows.
Interrupt Service Routine for Interrupt IN Transactions in DMA Mode
Unmask (CHHLTD)
if (CHHLTD)
{
if (XFERCOMPL)
{
Reset Error Count
Mask ACK
if (Transfer Done)
{
De-allocate Channel
}
else
{
Re-initialize Channel (in next b_interval - 1 Frame)
}
}
else if (STALL or BBLERR)
{
Reset Error Count
Mask ACK
De-allocate Channel
}
else if (NAK or DATATGLERR or FRMOVRUN)
{
Mask ACK
Re-initialize Channel (in next b_interval - 1 Frame)
if (DATATGLERR or NAK)
{
Reset Error Count
}
}
else if (XACTERR)
{
if (Error_count == 2)
{
De-allocate Channel
}
else
{
Increment Error Count
Unmask ACK
Re-initialize Channel (in next b_interval - 1 Frame)
}
}
}
else if (ACK)
{
Reset Error Count
Mask ACK
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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