EFM32WG Datasheet, PDF (206/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

14.3.19 Control Signal Polarity
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It is possible to individually configure the control signals to be active high/low by setting or clearing the
appropriate bits in the EBI_POLARITY register. When the ITS bitfield in the EBI_CTRL register is set to
0, the polarities defined in the EBI_POLARITY register applies to all 4 memory banks. When ITS is set
to 1 each memory bank uses an individual polarity definition. In this case register EBI_POLARITY only
applies to bank 0. Timing for bank n is then defined in the EBI_POLARITYn register.
The TFT control signals can also be individually configured to be active high/low by setting or clearing
the appropriate bits in the EBI_TFTPOLARITY register.
14.3.20 Pin Configuration
In order to give the EBI access to the external pins of the EFM32WG, the GPIO must be configured
accordingly. The lines must be set to Push-Pull, which is described in detail in the GPIO section.
All the EBI pins are enabled in the EBI_ROUTE register. The EBI_AD, EBI_WEn and EBI_REn pins
are all enabled by the EBIPEN bit, the EBI_CSn pins are enabled by the corresponding CSxPEN bit,
the EBI_ALE pin is enabled by the ALEPEN bit , the EBI_BL pins are enabled by the BLPEN bit, the
EBI_NANDWEn and EBI_NANDREn pins are enabled by the NANDPEN bit, the TFT pins EBI_DCLK,
EBI_VSYNC and EBI_HSYNC are all enabled by the TFTPEN bit, the EBI_DATAEN pin is enabled
by the DATAENPEN bit, the EBI_CSTFT pin is enabled by the CSTFTPEN bit, the EBI_A pins are
enabled by the ALB and APEN bitfields, and the EBI_ARDY pin is enabled by the ARDYPEN bit of the
EBI_ROUTE register.
For some of the EBI pins, alternative pin locations can be chosen by setting the LOCATION bitfield in
the EBI_ROUTE register. These alternative locations are specified in the datasheet.
14.3.21 Interrupts
The TFT controller has 6 separate interrupt flags (VSYNC, HSYNC, VBPORCH, VFPORCH, DDEMPTY,
DDJIT) in EBI_IF.
The VSYNC, HSYNC, VBPORCH, and VFPORCH interrupt flags indicate various synchronization points
during the display of a frame. Figure 14.46 (p. 207) shows the timing of the VSYNC, HSYNC,
VBPORCH, and VFPORCH interrupt flags. The VSYNC and HSYNC flags are set at the beginning of
a frame and at the beginning of a line respectively. The VBPORCH and VFPORCH flags are set at the
end of the vertical back porch and at the beginning of the vertical front porch respectively (provided that
the related porch is defined with a non-zero width).
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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