EFM32WG Datasheet, PDF (421/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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16.3.7.3 Reset State
After a reset, the state of the I²C-bus is unknown. To avoid interrupting transfers on the I²C-bus after
a reset of the I²C module or the entire MCU, the I²C-bus is assumed to be busy when coming out of a
reset, and the BUSY flag in I2Cn_STATUS is thus set. To be able to carry through master operations
on the I²C-bus, the bus must be idle.
The bus goes idle when a STOP condition is detected on the bus, but on buses with little activity, the
time before the I²C module detects that the bus is idle can be significant. There are two ways of assuring
that the I²C module gets out of the busy state.
• Use the ABORT command in I2Cn_CMD. When the ABORT command is issued, the I²C module is
instructed that the bus is idle. The I²C module can then initiate master operations.
• Use the Bus Idle Timeout. When SCL has been high for a long period of time, it is very likely that the
bus is idle. Set BITO in I2Cn_CTRL to an appropriate timeout period and set GIBITO in I2Cn_CTRL.
If activity has not been detected on the bus within the timeout period, the bus is then automatically
assumed idle, and master operations can be initiated.
Note
If operating in slave mode, the above approach is not necessary.
16.3.7.4 Master Transmitter
To transmit data to a slave, the master must operate as a master transmitter. Table 16.4 (p. 422)
shows the states the I²C module goes through while acting as a master transmitter. Every state where
an interaction is required has the possible interactions listed, along with the result of the interactions.
The table also shows which interrupt flags are set in the different states. The interrupt flags enclosed
in parenthesis may be set. If the BUSHOLD interrupt in I2Cn_IF is set, the module is waiting for an
interaction, and the bus is frozen. The value of I2Cn_STATE will be equal to the values given in the table
when the BUSHOLD interrupt flag is set, and can be used to determine which interaction is required to
make the transmission continue.
The interrupt flag START in I2Cn_IF is set when the I²C module transmits the START.
A master operation is started by issuing a START command by setting START in I2Cn_CMD. ADDR
+W, i.e. the address of the slave to address + the R/W bit is then required by the I²C module. If this
is not available in the transmit buffer, then the bus is held and the BUSHOLD interrupt flag is set. The
value of I2Cn_STATE will then be 0x57. As seen in the table, the I²C module also stops in this state if
the address is not available after a repeated start condition.
To continue, write a byte to I2Cn_TXDATA with the address of the slave in the 7 most significant bits
and the least significant bit cleared (ADDR+W). This address will then be transmitted, and the slave will
reply with an ACK or a NACK. If no slave replies to the address, the response will also be NACK. If
the address was acknowledged, the master now has four choices. If another byte is made available in
I2Cn_TXDATA, this byte is transmitted. The master can also stop the transmission by sending a STOP,
it can send a repeated start by sending START, or it can send a STOP and then a START as soon
as possible.
If a NACK was received, the master has to issue a CONT command in addition to providing data in order
to continue transmission. This is not standard I²C, but is provided for flexibility. The rest of the options
are similar to when an ACK was received.
If a new byte was transmitted, an ACK or NACK is received after the transmission of the byte, and the
master has the same options as for when the address was sent.
The master may lose arbitration at any time during transmission. In this case, the ARBLOST interrupt flag
in I2Cn_IF is set. If the arbitration was lost during the transfer of an address, and SLAVE in I2Cn_CTRL
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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