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15.4.3.6.9 Interrupt OUT Transactions in Slave Mode
To initialize the core after power-on reset, the application must follow the sequence in Overview:
Programming the Core (p. 246) . Before it can communicate with the connected device, it must
initialize a channel as described in Channel Initialization (p. 252) . See Figure 15.10 (p. 256) and
Figure 15.11 (p. 256) for read or write data to and from the FIFO in Slave mode.
A typical interrupt OUT operation in Slave mode is shown in Figure 15.15 (p. 268) . See channel 1
(ch_1). The assumptions are:
• The application is attempting to send one packet in every frame (up to 1 maximum packet size),
starting with the odd frame (transfer size = 1,024 bytes).
• The Periodic Transmit FIFO can hold one packet.
• Periodic Request Queue depth = 4.
15.4.3.6.9.1 Normal Interrupt OUT Operation
The sequence of operations in Figure 15.15 (p. 268) is as follows:
1. Initialize and enable channel 1 as explained in Channel Initialization (p. 252) . The application must
set the USB_HC1_CHAR.ODDFRM bit.
2. Write the first packet for channel 1. For a high-bandwidth interrupt transfer, the application must write
the subsequent packets up to MC (maximum number of packets to be transmitted in the next frame
times before switching to another channel).
3. Along with the last DWORD write of each packet, the host writes an entry to the Periodic Request
Queue.
4. The host attempts to send an OUT token in the next (odd) frame.
5. The host generates an XFERCOMPL interrupt as soon as the last packet is transmitted successfully.
6. In response to the XFERCOMPL interrupt, reinitialize the channel for the next transfer.
15.4.3.6.9.2 Handling Interrupts
The channel-specific interrupt service routine for Interrupt OUT transactions in Slave mode is shown in
the following flow:
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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