EFM32WG Datasheet, PDF (357/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
9
HNPCAP
0
RW
HNP-Capable (host and device)
The application uses this bit to control the core's HNP capabilities. Set to enable HNP capability.
8
SRPCAP
0
RW
SRP-Capable (host and device)
The application uses this bit to control the core's SRP capabilities. If the core operates as a non-SRP-capable B-device, it cannot
request the connected A-device (host) to activate VBUS and start a session. Set to enable SRP capability.
7:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
5
FSINTF
0
RW
Full-Speed Serial Interface Select (host and device)
Always write this bit to 0.
4:3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2:0
TOUTCAL
0x0
RW
Timeout Calibration (host and device)
Always write this field to 0.
15.6.12 USB_GRSTCTL - Reset Register
The application uses this register to reset various hardware features inside the core.
Offset
0x3C010
Bit Position
Reset
Access
Name
Bit
31
30
29:11
10:6
5
Name
Reset
Access Description
AHBIDLE
1
R
AHB Master Idle (host and device)
Indicates that the AHB Master State Machine is in the IDLE condition.
DMAREQ
0
R
DMA Request Signal (host and device)
Indicates that the DMA request is in progress. Used for debug.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
TXFNUM
0x00
RW
TxFIFO Number (host and device)
This is the FIFO number that must be flushed using the TxFIFO Flush bit. This field must not be changed until the core clears the
TxFIFO Flush bit.
Value
0
1
2
3
4
5
6
16
Mode
F0
F1
F2
F3
F4
F5
F6
FALL
Description
Host mode: Non-periodic TxFIFO flush.
Device: Tx FIFO 0 flush
Host mode: Periodic TxFIFO flush.
Device: TXFIFO 1 flush.
Device mode: TXFIFO 2 flush.
Device mode: TXFIFO 3 flush.
Device mode: TXFIFO 4 flush.
Device mode: TXFIFO 5 flush.
Device mode: TXFIFO 6 flush.
Flush all the transmit FIFOs in device or host mode.
TXFFLSH
0
RW1
TxFIFO Flush (host and device)
This bit selectively flushes a single or all transmit FIFOs, but cannot do so if the core is in the midst of a transaction. The application
must write this bit only after checking that the core is neither writing to the TxFIFO nor reading from the TxFIFO. NAK Effective
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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