EFM32WG Datasheet, PDF (273/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Re-initialize Channel (in next b_interval - 1 Frame)
}
}
else if (STALL)
{
Transfer Done = 1
Reset Error Count
Mask ACK
De-allocate Channel
}
else if (NAK or FRMOVRUN)
{
Mask ACK
Rewind Buffer Pointers
Re-initialize Channel (in next b_interval - 1 Frame)
if (NAK)
{
Reset Error Count
}
}
else if (XACTERR)
{
if (Error_count == 2)
{
De-allocate Channel
}
else
{
Increment Error Count
Rewind Buffer Pointers
Unmask ACK
Re-initialize Channel (in next b_interval - 1 Frame)
}
}
}
else if (ACK)
{
Reset Error Count
Mask ACK
}
As soon as the channel is enabled, the core attempts to fetch and write data packets, in maximum
packet size multiples, to the transmit FIFO when the space is available in the transmit FIFO and the
Request queue. The core stops fetching as soon as the last packet is fetched (the number of packets
is determined by the MC field of the USB_HCx_CHAR register).
15.4.3.6.12 Interrupt IN Transactions in DMA Mode
To initialize the core after power-on reset, the application must follow the sequence in Overview:
Programming the Core (p. 246) . Before it can communicate with the connected device, it must initialize
a channel as described in Channel Initialization (p. 252) .
A typical interrupt IN operation in DMA mode is shown in Figure 15.16 (p. 272) . See channel 2 (ch_2).
The assumptions are:
• The application is attempting to receive one packet in every frame (up to 1 maximum packet size of
1,024 bytes).
• The receive FIFO can hold at least one maximum-packet-size packet and two status DWORDs per
packet (1,032 bytes for FS).
• Periodic Request Queue depth = 4.
15.4.3.6.12.1 Normal Interrupt IN Operation
The sequence of operations in Figure 15.16 (p. 272) (channel 2) is as follows:
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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