EFM32WG Datasheet, PDF (798/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

Offset
0x000
Reset
Access
Name
...the world's most energy friendly microcontrollers
Bit Position
Bit
31:24
23
22:3
2:1
0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
DSC
0
RW
Direct Segment Control
This bit enables direct control over bias levels for each SEG/COM line.
Value
0
1
Description
DSC disable
DSC enable
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
UDCTRL
0x0
RW
Update Data Control
These bits control how data from the SEGDn registers are transferred to the LCD driver.
Value
0
1
2
Mode
REGULAR
FCEVENT
FRAMESTART
Description
The data transfer is controlled by SW. Transfer is performed as soon as possible
The data transfer is done at the next event triggered by the Frame Counter
The data transfer is done continuously at every LCD frame start
EN
0
RW
LCD Enable
When this bit is set, the LCD driver is enabled and the driver will start outputting waveforms on the com/segment lines.
33.5.2 LCD_DISPCTRL - Display Control Register
Offset
0x004
Reset
Access
Bit Position
Name
Bit
31:23
22
21
20:18
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
MUXE
0
RW
This bit redefines the meaning of the MUX field.
Extended Mux Configuration
Value
0
1
Mode
MUX
MUXE
Description
Multiplex mode determined by MUX field.
Mux extended mode. Extends the meaning of the MUX field.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
VBLEV
0x3
RW
Voltage Boost Level
These bits control Voltage Boost level. Please refer to datasheet for further details of the boost levels.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
798
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