EFM32WG Datasheet, PDF (560/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

21.4 Register Map
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The offset register address is relative to the registers base address.
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
Name
RTC_CTRL
RTC_CNT
RTC_COMP0
RTC_COMP1
RTC_IF
RTC_IFS
RTC_IFC
RTC_IEN
RTC_FREEZE
RTC_SYNCBUSY
Type
RW
RWH
RW
RW
R
W1
W1
RW
RW
R
Description
Control Register
Counter Value Register
Compare Value Register 0
Compare Value Register 1
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
Interrupt Enable Register
Freeze Register
Synchronization Busy Register
21.5 Register Description
21.5.1 RTC_CTRL - Control Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 21) .
Offset
0x000
Reset
Access
Bit Position
Name
Bit
31:3
2
1
0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
COMP0TOP
0
RW
Compare Channel 0 is Top Value
When set, the counter is cleared in the clock cycle after a compare match with compare channel 0.
Value
0
1
Mode
DISABLE
ENABLE
Description
The top value of the RTC is 16777215 (0xFFFFFF)
The top value of the RTC is given by COMP0
DEBUGRUN
0
RW
Set this bit to enable the RTC to keep running in debug.
Debug Mode Run Enable
Value
0
1
Description
RTC is frozen in debug mode
RTC is running in debug mode
EN
0
RW
RTC Enable
When this bit is set, the RTC is enabled and counts up. When cleared, the counter register CNT is reset.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
560
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