EFM32WG Datasheet, PDF (261/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

}
else if (ACK)
{
Reset Error Count
Mask ACK
}
else if (DATATGLERR)
{
Reset Error Count
}
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15.4.3.6.6 Control Transactions in DMA Mode
Setup, Data, and Status stages of a control transfer must be performed as three separate transfers.
Setup- and Data- or Status-stage OUT transactions are performed similarly to the bulk OUT transactions
explained in Bulk and Control OUT/SETUP Transactions in DMA Mode(p. 261) . Data- or Status-
stage IN transactions are performed similarly to the bulk IN transactions explained in Bulk and Control
IN Transactions in DMA Mode (p. 265) . For all three stages, the application is expected to set the
USB_HC1_CHAR.EPTYPE field to Control. During the Setup stage, the application is expected to set
the USB_HC1_TSIZ.PID field to SETUP.
15.4.3.6.7 Bulk and Control OUT/SETUP Transactions in DMA Mode
To initialize the core after power-on reset, the application must follow the sequence in Overview:
Programming the Core (p. 246) . Before it can communicate with the connected device, it must initialize
a channel as described in Channel Initialization (p. 252) .
This section discusses the following topics:
• Overview (p. 261)
• Normal Bulk and Control OUT/SETUP Operations (p. 261)
• NAK Handling with DMA (p. 261)
• Handling Interrupts (p. 263)
15.4.3.6.7.1 Overview
• The application is attempting to send two maximum-packet-size packets (transfer size = 1,024 bytes).
• The Non-periodic Transmit FIFO can hold two packets (128 bytes for FS).
• The Non-periodic Request Queue depth = 4.
15.4.3.6.7.2 Normal Bulk and Control OUT/SETUP Operations
The sequence of operations in Figure 15.12 (p. 258) is as follows:
1. Initialize and enable channel 1 as explained in Channel Initialization (p. 252) .
2. The host starts fetching the first packet as soon as the channel is enabled. For DMA mode, the host
uses the programmed DMA address to fetch the packet.
3. After fetching the last DWORD of the second (last) packet, the host masks channel 1 internally for
further arbitration.
4. The host generates a CHHLTD interrupt as soon as the last packet is sent.
5. In response to the CHHLTD interrupt, de-allocate the channel for other transfers.
The channel-specific interrupt service routine for bulk and control OUT/SETUP transactions in DMA
mode is shown in Handling Interrupts (p. 263) .
15.4.3.6.7.3 NAK Handling with DMA
1. The Host sends a Bulk OUT Transaction.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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