EFM32WG Datasheet, PDF (393/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
10:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
7
TXFEMP
1
R
Transmit FIFO Empty
This interrupt is asserted when the TxFIFO for this endpoint is either half or completely empty. The half or completely empty status
is determined by the TxFIFO Empty Level bit in the Core AHB Configuration register (USB_GAHBCFG.NPTXFEMPLVL).
6
INEPNAKEFF
0
RW1
IN Endpoint NAK Effective
Applies to periodic IN endpoints only. This bit can be cleared when the application clears the IN endpoint NAK by writing to
USB_DIEPx_CTL.CNAK. This interrupt indicates that the core has sampled the NAK bit set (either by the application or by the
core). The interrupt indicates that the IN endpoint NAK bit set by the application has taken effect in the core. This interrupt does not
guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.
5
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
4
INTKNTXFEMP
0
RW1
IN Token Received When TxFIFO is Empty
Applies to non-periodic IN endpoints only. Indicates that an IN token was received when the associated TxFIFO (periodic/non-
periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.
3
TIMEOUT
0
RW1
Timeout Condition
Applies only to Control IN endpoints. Indicates that the core has detected a timeout condition on the USB for the last IN token on
this endpoint.
2
AHBERR
0
RW1
AHB Error
This is generated only in DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding
endpoint DMA address register to get the error address.
1
EPDISBLD
0
RW1
Endpoint Disabled Interrupt
This bit indicates that the endpoint is disabled per the application's request.
0
XFERCOMPL
0
RW1
Transfer Completed Interrupt
This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.
15.6.57 USB_DIEPx_TSIZ - Device IN Endpoint x+1 Transfer Size Register
The application must modify this register before enabling the endpoint. Once the endpoint is enabled
using Endpoint Enable bit of the Device Endpoint x+1 Control register (USB_DIEPx_CTL.EPENA), the
core modifies this register. The application can only read this register once the core has cleared the
Endpoint Enable bit.
Offset
0x3C930
Bit Position
Reset
Access
Name
Bit
31
30:29
28:19
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
MC
0x0
RW
Multi Count
For periodic IN endpoints, this field indicates the number of packets that must be transmitted per frame on the USB. The core uses
this field to calculate the data PID for isochronous IN endpoints.
PKTCNT
0x000
RW
Packet Count
Indicates the total number of USB packets that constitute the Transfer Size amount of data. This field is decremented every time a
packet (maximum size or short packet) is read from the TxFIFO.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
393
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