EFM32WG Datasheet, PDF (147/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
0
HFRCORDY
0
W1
HFRCO Ready Interrupt Flag Clear
Write to 1 to clear the HFRCO Ready Interrupt Flag.
11.5.16 CMU_IEN - Interrupt Enable Register
Offset
0x03C
Reset
Access
Bit Position
Name
Bit
Name
Reset
Access Description
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
7
USBCHFCLKSEL
0
RW
USBC HFCLK Selected Interrupt Enable
Set to enable the USBC HFCLK Selected Interrupt.
6
CALOF
0
RW
Calibration Overflow Interrupt Enable
Set to enable the Calibration Overflow Interrupt.
5
CALRDY
0
RW
Calibration Ready Interrupt Enable
Set to enable the Calibration Ready Interrupt.
4
AUXHFRCORDY
0
RW
AUXHFRCO Ready Interrupt Enable
Set to enable the AUXHFRCO Ready Interrupt.
3
LFXORDY
0
RW
LFXO Ready Interrupt Enable
Set to enable the LFXO Ready Interrupt.
2
LFRCORDY
0
RW
LFRCO Ready Interrupt Enable
Set to enable the LFRCO Ready Interrupt.
1
HFXORDY
0
RW
HFXO Ready Interrupt Enable
Set to enable the HFXO Ready Interrupt.
0
HFRCORDY
0
RW
HFRCO Ready Interrupt Enable
Set to enable the HFRCO Ready Interrupt.
11.5.17 CMU_HFCORECLKEN0 - High Frequency Core Clock Enable
Register 0
Offset
0x040
Reset
Access
Bit Position
Name
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
147
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