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Figure 20.16. TIMER Output Logic
COIST
Out put
Com pare/
PWM x
OUTINV
0
1
TIMn _CCx
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20.3.2.4.1 Frequency Generation (FRG)
Frequency generation (see Figure 20.17 (p. 529) ) can be achieved in compare mode by:
• Setting the counter in up-count mode
• Enabling buffering of the TOP value.
• Setting the CC channels overflow action to toggle
Figure 20.17. TIMER Up-count Frequency Generation
TIMERn _TOP
0
TIMERn _CCx _CCV
The output frequency is given by Equation 20.2 (p. 529)
TIMER Up-count Frequency Generation Equation
f_FRG = f_HFPERCLK/ ( 2^(PRESC + 1) x (TOP + 1) x 2)
(20.2)
20.3.2.5 Pulse-Width Modulation (PWM)
In PWM mode, TIMERn_CCx_CCV is buffered to avoid glitches in the output. The settings in the
Compare Output Action configuration bits are ignored in PWM mode and PWM generation is only
supported for up-count and up/down-count mode.
20.3.2.6 Up-count (Single-slope) PWM
If the counter is set to up-count and the Compare/Capture channel is put in PWM mode, single slope
PWM output will be generated (see Figure 20.18 (p. 529) ). In up-count mode the PWM period is TOP
+1 cycles and the PWM output will be high for a number of cycles equal to TIMERn_CCx_CCV. This
means that a constant high output is achieved by setting TIMER_CCx to TOP+1 or higher. The PWM
resolution (in bits) is then given by Equation 20.3 (p. 529) .
Figure 20.18. TIMER Up-count PWM Generation
TIMERn _TOP
TIMERn _CCx _CCV
0
TIMn _CCx
Ov e r f l o w
Com pare m at ch
Buffer update
TIMER Up-count PWM Resolution Equation
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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