EFM32WG Datasheet, PDF (804/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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33.5.11 LCD_IEN - Interrupt Enable Register
Offset
0x028
Reset
Access
Bit Position
Name
Bit
Name
Reset
Access Description
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
0
FC
0
RW
Frame Counter Interrupt Enable
Set to enable interrupt on frame counter interrupt flag.
33.5.12 LCD_SEGD0L - Segment Data Low Register 0 (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 21) .
Offset
0x040
Bit Position
Reset
Access
Name
Bit
Name
Reset
Access Description
31:0
SEGD0L
0x00000000
RW
COM0 Segment Data Low
This register contains segment data for segment lines 0-31 for COM0.
33.5.13 LCD_SEGD1L - Segment Data Low Register 1 (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 21) .
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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