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6. To perform a data OUT transfer in the status OUT phase, the application must program the core as
described in OUT Data Transfers in Slave and DMA Modes (p. 285) .
• The application must program the USB_DCFG.NZSTSOUTHSHK handshake field to a proper
setting before transmitting an data OUT transfer for the Status stage.
• In DMA mode, the application must reprogram the USB_DOEPx_DMAADDR register to receive
the control OUT data packet to a different memory location.
7. Assertion of the USB_DOEPx_INT.XFERCOMPL interrupt indicates completion of the status OUT
phase of the control transfer. This marks the successful completion of the control read transfer.
• To transfer a new SETUP packet in DMA mode, the application must re-enable the control OUT
endpoint as explained in OUT Data Transfers in Slave and DMA Modes (p. 285) .
• USB_DOEPx_CTL.EPENA = 1
15.4.4.2.2.3 Two-Stage Control Transfers (SETUP/Status IN)
This section describes two-stage control transfers.
Application Programming Sequence
1. Assertion of the USB_DOEPx_INT.SETUP interrupt indicates that a valid SETUP packet has
been transferred to the application. See OUT Data Transfers in Slave and DMA Modes (p.
285) for more detail. To receive the next SETUP packet, the application must reprogram the
USB_DOEPx_TSIZ.SUPCNT field to 3 at the end of the Setup stage.
2. Decode the last SETUP packet received before the assertion of the SETUP interrupt. If the packet
indicates a two-stage control command, the application must do the following.
• To transfer a new SETUP packet in DMA mode, the application must re-enable the control OUT
endpoint. See OUT Data Transfers in Slave and DMA Modes (p. 285) for details.
• USB_DOEPx_CTL.EPENA = 1
• Depending on the type of Setup command received, the application can be required to program
registers in the core to execute the received Setup command.
3. For the status IN phase, the application must program the core described in Generic Non-Periodic
(Bulk and Control) IN Data Transfers Without Thresholding in DMA and Slave Mode(p. 308) to
perform a data IN transfer.
4. Assertion of the USB_DIEPx_INT.XFERCOMPL interrupt indicates the completion of the status IN
phase of the control transfer.
5. The previous step must be repeated until the USB_DIEPx_INT.XFERCOMPL interrupt is detected on
the endpoint, marking the completion of the two-stage control transfer.
Example: Two-Stage Control Transfer
These notes refer to Figure 15.20 (p. 290) .
1. SETUP packet #1 is received on the USB and is written to the receive FIFO, and the core responds
with an ACK handshake. This handshake is lost and the host detects a timeout.
2. The SETUP packet in the receive FIFO results in a USB_GINTSTS.RXFLVL interrupt to the
application, causing the application to empty the receive FIFO.
3. SETUP packet #2 on the USB is written to the receive FIFO, and the core responds with an ACK
handshake.
4. The SETUP packet in the receive FIFO sends the application the USB_GINTSTS.RXFLVL interrupt
and the application empties the receive FIFO.
5. After the second SETUP packet, the host sends a control IN token for the status phase. The core
issues a NAK response to this token, and writes a Setup Stage Done entry to the receive FIFO. This
entry results in a USB_GINTSTS.RXFLVL interrupt to the application, which empties the receive FIFO.
After reading out the Setup Stage Done DWORD, the core asserts the USB_DOEPx_INT.SETUP
packet interrupt to the application.
6. On this interrupt, the application processes SETUP Packet #2, decodes it to be a two-stage control
command, and clears the control IN NAK bit.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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