EFM32WG Datasheet, PDF (377/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
0
XFERCOMPL
0
RW1
Transfer Completed
Transfer completed normally without any errors. This bit can be set only by the core and the application should write 1 to clear it.
15.6.37 USB_HCx_INTMSK - Host Channel x Interrupt Mask Register
This register reflects the mask for each channel status described in the USB_CHx_INT.
Offset
0x3C50C
Reset
Access
Bit Position
Name
Bit
31:11
10
9
8
7
6
5
4
3
2
1
0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
DATATGLERRMSK
0
RW
Data Toggle Error Mask
Set to unmask DATATGLERR interrupt.
FRMOVRUNMSK
0
RW
Frame Overrun Mask
Set to unmask FRMOVRUN interrupt.
BBLERRMSK
0
RW
Babble Error Mask
Set to unmask BBLERR interrupt.
XACTERRMSK
0
RW
Transaction Error Mask
Set to unmask XACTERR interrupt.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
ACKMSK
0
RW
ACK Response Received/Transmitted Interrupt Mask
Set to unmask ACK interrupt.
NAKMSK
0
RW
NAK Response Received Interrupt Mask
Set to unmask NAK interrupt.
STALLMSK
0
RW
STALL Response Received Interrupt Mask
Set to unmask STALL interrupt.
AHBERRMSK
0
RW
AHB Error Mask
Set to unmask AHBERR interrupt.
CHHLTDMSK
0
RW
Channel Halted Mask
Set to unmask CHHLTD interrupt.
XFERCOMPLMSK
0
RW
Transfer Completed Mask
Set to unmask XFERCOMPL interrupt.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
377
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