EFM32WG Datasheet, PDF (13/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

...the world's most energy friendly microcontrollers
• 1.25 DMIPS/MHz
• Memory Protection Unit
• Up to 8 protected memory regions
• 24-bit System Tick Timer for Real-Time Operating System (RTOS)
• Excellent 32-bit migration choice for 8/16 bit architecture based designs
• Simplified stack-based programmer's model is compatible with traditional ARM architecture and
retains the programming simplicity of legacy 8- and 16-bit architectures
• Unaligned data storage and access
• Continuous storage of data requiring different byte lengths
• Data access in a single core clock cycle
• Integrated power modes
• Sleep Now mode for immediate transfer to low power state
• Sleep on Exit mode for entry into low power state after the servicing of an interrupt
• Ability to extend power savings to other system components
• Optimized for low latency, nested interrupts
4.3 Functional Description
For a full functional description of the ARM Cortex-M4 (r0p1) implementation in the EFM32WG family,
the reader is referred to the ARM Cortex-M4 Devices Generic User Guide.
4.3.1 Interrupt Operation
Figure 4.1. Interrupt Operation
Module
IFS[ n]
IFC[ n]
IEN[ n]
In t er r u p t
condition
set clear
IF[ n]
Cort ex-M4 NVIC
SETENA[ n] /CLRENA[ n]
Active interrupt
IRQ
In t er r u p t
request
set
clear
SETPEND[ n] /CLRPEND[ n]
Soft ware generat ed int errupt
The EFM32WG devices have up to 31 interrupt request lines (IRQ) which are connected to the Cortex-
M4. Each of these lines (shown in Table 4.1 (p. 13) ) are connected to one or more interrupt flags in
one or more modules. The interrupt flags are set by hardware on an interrupt condition. It is also possible
to set/clear the interrupt flags through the IFS/IFC registers. Each interrupt flag is then qualified with its
own interrupt enable bit (IEN register), before being OR'ed with the other interrupt flags to generate the
IRQ. A high IRQ line will set the corresponding pending bit (can also be set/cleared with the SETPEND/
CLRPEND bits in ISPR0/ICPR0) in the Cortex-M4 NVIC. The pending bit is then qualified with an enable
bit (set/cleared with SETENA/CLRENA bits in ISER0/ICER0) before generating an interrupt request to
the core. Figure 4.1 (p. 13) illustrates the interrupt system. For more information on how the interrupts
are handled inside the Cortex-M4, the reader is referred to the ARM Cortex-M4 Devices Generic User
Guide.
Table 4.1. Interrupt Request Lines (IRQ)
IRQ #
0
1
2
3
4
Source
DMA
GPIO_EVEN
TIMER0
USART0_RX
USART0_TX
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
13
www.energymicro.com