EFM32WG Datasheet, PDF (54/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

Figure 8.2. Polling flowchart
St art polling
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Is there
a channel
No
request ?
Yes
Are any
channel requests
using a high priority- ^No
level ?
Yes
Select channel t hat has
the lowest channel
num ber and is set to
high priority-level
Select channel t hat has
the lowest channel
num ber
St art DMA t ransfer
8.4.2.3 DMA cycle types
The cycle_ctrl bits control how the controller performs a DMA cycle. You can set the cycle_ctrl bits as
Table 8.3 (p. 54) lists.
Table 8.3. DMA cycle types
cycle_ctrl
b000
b001
b010
b011
b100
b101
b110
b111
Description
Channel control data structure is invalid
Basic DMA transfer
Auto-request
Ping-pong
Memory scatter-gather using the primary data structure
Memory scatter-gather using the alternate data structure
Peripheral scatter-gather using the primary data structure
Peripheral scatter-gather using the alternate data structure
Note
The cycle_ctrl bits are located in the channel_cfg memory location that Section 8.4.3.3 (p.
65) describes.
For all cycle types, the controller arbitrates after 2^R DMA transfers. If you set a low-priority channel with
a large 2^R value then it prevents all other channels from performing a DMA transfer, until the low-priority
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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