EFM32WG Datasheet, PDF (35/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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7.3.5.1 One Wait-state Access
After reset, the HFCORECLK is normally 14 MHz from the HFRCO and the MODE field of the
MSC_READCTRL register is set to WS1 (one wait-state). The reset value must be WS1 as an
uncalibrated HFRCO may produce a frequency higher than 16 MHz. Software must not select a zero
wait-state mode unless the clock is guaranteed to be 16 MHz or below, otherwise the resulting behavior
is undefined. If a HFCORECLK frequency above 16 MHz is to be set by software, the MODE field of
the MSC_READCTRL register must be set to WS1 or WS1SCBTP before the core clock is switched to
the higher frequency clock source.
When changing to a lower frequency, the MODE field of the MSC_READCTRL register must be set to
WS0 or WS0SCBTP only after the frequency transition has completed. If the HFRCO is used, wait until
the oscillator is stable on the new frequency. Otherwise, the behavior is unpredictable.
To run at a frequency higher than 32 MHz, WS2 or WS2SCBTP must be selected to insert two wait-
states for every flash access.
7.3.5.2 Zero Wait-state Access
At 16 MHz and below, read operations from flash may be performed without any wait-states. Zero wait-
state access greatly improves code execution performance at frequencies from 16 MHz and below.
By default, the Cortex-M4 uses speculative prefetching and If-Then block folding to maximize code
execution performance at the cost of additional flash accesses and energy consumption.
7.3.5.3 Operation Above 32 MHz
To run at frequencies higher than 32 MHz, MODE in MSC_READCTRL must be set to WS2 or
WS2SCBTP.
7.3.5.4 Suppressed Conditional Branch Target Prefetch (SCBTP)
MSC offers a special instruction fetch mode which optimizes energy consumption by cancelling Cortex-
M4 conditional branch target prefetches. Normally, the Cortex-M4 core prefetches both the next
sequential instruction and the instruction at the branch target address when a conditional branch
instruction reaches the pipeline decode stage. This prefetch scheme improves performance while one
extra instruction is fetched from memory at each conditional branch, regardless of whether the branch is
taken or not. To optimize for low energy, the MSC can be configured to cancel these speculative branch
target prefetches. With this configuration, energy consumption is more optimal, as the branch target
instruction fetch is delayed until the branch condition is evaluated.
The performance penalty with this mode enabled is source code dependent, but is normally less than
1% for core frequencies from 16 MHz and below. To enable the mode at frequencies from 16 MHz and
below write WS0SCBTP to the MODE field of the MSC_READCTRL register. For frequencies above 16
MHz, use the WS1SCBTP mode, and for frequencies above 32 MHz, use the WS2SCBTP mode. An
increased performance penalty per clock cycle must be expected compared to WS0SCBTP mode. The
performance penalty in WS1SCBTP/WS2SCBTP mode depends greatly on the density and organization
of conditional branch instructions in the code.
7.3.5.5 Cortex-M4 If-Then Block Folding
The Cortex-M4 offers a mechanism known as if-then block folding. This is a form of speculative
prefetching where small if-then blocks are collapsed in the prefetch buffer if the condition evaluates to
false. The instructions in the block then appear to execute in zero cycles. With this scheme, performance
is optimized at the cost of higher energy consumption as the processor fetches more instructions from
memory than it actually executes. To disable the mode, write a 1 to the DISFOLD bit in the NVIC Auxiliary
Control Register; see the Cortex-M4 Technical Reference Manual for details. Normally, it is expected
that this feature is most efficient at core frequencies above 16 MHz. Folding is enabled by default.
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