EFM32WG Datasheet, PDF (474/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
Sets the number of clock periods in a UART bit-period. More clock cycles gives better robustness, while less clock cycles gives
better performance.
Value
0
1
2
3
Mode
X16
X8
X6
X4
Description
Regular UART mode with 16X oversampling in asynchronous mode
Double speed with 8X oversampling in asynchronous mode
6X oversampling in asynchronous mode
Quadruple speed with 4X oversampling in asynchronous mode
4
MPAB
0
RW
Multi-Processor Address-Bit
Defines the value of the multi-processor address bit. An incoming frame with its 9th bit equal to the value of this bit marks the frame
as a multi-processor address frame.
3
MPM
0
RW
Multi-Processor Mode
Multi-processor mode uses the 9th bit of the USART frames to tell whether the frame is an address frame or a data frame.
Value
0
1
Description
The 9th bit of incoming frames has no special function
An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and
will result in the MPAB interrupt flag being set
2
CCEN
0
RW
Collision Check Enable
Enables collision checking on data when operating in half duplex modus.
Value
0
1
Description
Collision check is disabled
Collision check is enabled. The receiver must be enabled for the check to be performed
1
LOOPBK
0
RW
Loopback Enable
Allows the receiver to be connected directly to the USART transmitter for loopback and half duplex communication.
Value
0
1
Description
The receiver is connected to and receives data from U(S)n_RX
The receiver is connected to and receives data from U(S)n_TX
0
SYNC
0
RW
USART Synchronous Mode
Determines whether the USART is operating in asynchronous or synchronous mode.
Value
0
1
Description
The USART operates in asynchronous mode
The USART operates in synchronous mode
17.5.2 USARTn_FRAME - USART Frame Format Register
Offset
0x004
Reset
Access
Bit Position
Name
Bit
31:14
13:12
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
STOPBITS
0x1
RW
Determines the number of stop-bits used.
Stop-Bit Mode
Value
0
Mode
HALF
Description
The transmitter generates a half stop bit. Stop-bits are not verified by receiver
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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