EFM32WG Datasheet, PDF (138/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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11.5.3 CMU_HFPERCLKDIV - High Frequency Peripheral Clock Division
Register
Offset
0x008
Reset
Access
Bit Position
Name
Bit
31:9
8
7:4
3:0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
HFPERCLKEN
1
RW
HFPERCLK Enable
Set to enable the HFPERCLK.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
HFPERCLKDIV
0x0
RW
Specifies the clock divider for the HFPERCLK.
HFPERCLK Divider
Value
0
1
2
3
4
5
6
7
8
9
Mode
HFCLK
HFCLK2
HFCLK4
HFCLK8
HFCLK16
HFCLK32
HFCLK64
HFCLK128
HFCLK256
HFCLK512
Description
HFPERCLK = HFCLK.
HFPERCLK = HFCLK/2.
HFPERCLK = HFCLK/4.
HFPERCLK = HFCLK/8.
HFPERCLK = HFCLK/16.
HFPERCLK = HFCLK/32.
HFPERCLK = HFCLK/64.
HFPERCLK = HFCLK/128.
HFPERCLK = HFCLK/256.
HFPERCLK = HFCLK/512.
11.5.4 CMU_HFRCOCTRL - HFRCO Control Register
Offset
0x00C
Reset
Access
Bit Position
Name
Bit
31:17
16:12
11
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
SUDELAY
0x00
RW
HFRCO Start-up Delay
Always write this field to 0.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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