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7.5.2 MSC_READCTRL - Read Control Register
Offset
0x004
Reset
Access
Bit Position
Name
Bit
31:18
17:16
15:8
7
6
5
4
3
2:0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
BUSSTRATEGY
0x0
RW
Specify which master has low latency to bus matrix.
Strategy for bus matrix
Value
0
1
2
3
Mode
CPU
DMA
DMAEM1
NONE
Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RAMCEN
0
RW
RAM Cache Enable
Enable instruction caching for RAM in code-space.
EBICDIS
0
RW
External Bus Interface Cache Disable
Disable instruction cache for external bus interface.
ICCDIS
0
RW
Interrupt Context Cache Disable
Set this bit to automatically disable caching of vector fetches and instruction fetches in interrupt context. Cache lookup will still be
performed in interrupt context. When set, the performance counters will not count when these types of fetches occur.
AIDIS
0
RW
Automatic Invalidate Disable
When this bit is set the cache is not automatically invalidated when a write or page erase is performed.
IFCDIS
0
RW
Internal Flash Cache Disable
Disable instruction cache for internal flash memory.
MODE
0x1
RW
Read Mode
After reset, the core clock is 14 MHz from the HFRCO and the MODE field of MSC_READCTRL register is set to WS1. The reset
value is WS1 because the HFRCO may produce a frequency above 16 MHz before it is calibrated. WS1 or WS1SCBTP mode is
required for a frequency above 16 MHz. If software wants to set a core clock frequency above 16 MHz, this register must be set to
WS1 or WS1SCBTP before the core clock is switched to the higher frequency. When changing to a lower frequency, this register
can be set to WS0 or WS0SCBTP after the frequency transition has been completed. If the HFRCO is used as clock source, wait
until the oscillator is stable on the new frequency to avoid unpredictable behavior.
Value
0
1
2
Mode
WS0
WS1
WS0SCBTP
3
WS1SCBTP
4
WS2
5
WS2SCBTP
Description
Zero wait-states inserted in fetch or read transfers.
One wait-state inserted for each fetch or read transfer. This mode is required for a core
frequency above 16 MHz.
Zero wait-states inserted with the Suppressed Conditional Branch Target Prefetch
(SCBTP) function enabled. SCBTP saves energy by delaying the Cortex' conditional
branch target prefetches until the conditional branch instruction is in the execute stage.
When the instruction reaches this stage, the evaluation of the branch condition is
completed and the core does not perform a speculative prefetch of both the branch
target address and the next sequential address. With the SCBTP function enabled,
one instruction fetch is saved for each branch not taken, with a negligible performance
penalty.
One wait-state access with SCBTP enabled.
Two wait-states inserted for each fetch or read transfer. This mode is required for a
core frequency above 32 MHz.
Two wait-state access with SCBTP enabled.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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