EFM32WG Datasheet, PDF (183/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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EBI_NANDREn and EBI_NANDWEn the leading edge of the strobe can be moved half a clock period
later. Decreasing the length of the EBI_ALE strobe can be thought of as increasing the length of the
RDSETUP phase by the same amount. Similarly, decreasing the length of the EBI_REn, EBI_WEn,
EBI_NANDREn, EBI_NANDWEn strobes can be thought of as increasing the length of the RDSETUP
and WRSETUP phases. Note that the length of the ADDRSETUP, RDSTRB, and WRSTRB phases is still
1 or more internal clock cycles. For example, when HALFRE is set to 1 and RDSTRB is programmed to
2, the length of the RDSTRB phase is 2 cycles. The duration of the EBI_REn pulse is however decreased
by half a cycle to 1 1/2 cycles.
Figure 14.5 (p. 177) and Figure 14.6 (p. 177) respectively show read and write transactions in the
multiplexed 16-bit address, 16-bit data mode in which half strobes are enabled for EBI_ALE, EBI_REn
and EBI_WEn.
Figure 14.19. EBI Multiplexed Read Operation with Reduced Length Strobes
EBI_AD[ 15:0]
ADDRSETUP
(1, 2, 3, ...)
ADDR[ 16:1]
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
Z
DATA[ 15:0]
Z
EBI_ALE
EBI_CSn
EBI_REn
(½ , 1 ½ , 2 ½ , ...)
(½ )
(½ )
(½ , 1 ½ , 2 ½ , ...)
Figure 14.20. EBI Multiplexed Write Operation with Reduced Length Strobes
EBI_AD[ 15:0]
ADDRSETUP
(1, 2, 3, ...)
ADDR[ 16:1]
ADDRHOLD
(0, 1, 2, ...)
WRSETUP
(0, 1, 2, ...)
DATA[ 15:0]
WRSTRB
(1, 2, 3, ...)
WRHOLD
(0, 1, 2, ...)
Z
EBI_ALE
EBI_CSn
EBI_WEn
(½ , 1 ½ , 2 ½ , ...)
(½ )
(½ )
(½ , 1 ½ , 2 ½ , ...)
14.3.9 Bus turn-around and Idle cycles
The EBI_AD lines can be driven by either the EFM32WG or by the external device. Depending on the
characteristics of an external device, the RDHOLD should be programmed to ensure adequate bus turn-
around time. Default the EBI inserts an initial IDLE cycle, during which the EBI does not drive the EBI_AD
lines, after each external transaction. Furthermore, the EBI deasserts the EBI_CSn, EBI_REn, and
EBI_WEn lines during IDLE cycles. In case of subsequent IDLE cycles, after the initial one, the EBI will
drive the EBI_AD lines while keeping the EBI_CSn, EBI_REn, and EBI_WEn lines deasserted. The IDLE
state insertion is shown for two back-to-back read transactions in Figure 14.21 (p. 184) . In case that
the IDLE state provides the required bus turn-around time, the RDHOLD parameter can be programmed
to 0. For increased performance, the automatic IDLE state insertion can be prevented by setting the
NOIDLE/NOIDLEn bits in the EBI_CTRL register to 1. This scenario is shown in Figure 14.22 (p. 184)
for two back-to-back reads in a non-multiplexed addressing mode. Note that in case RDSETUP and
RDHOLD are both programmed to 0, then the EBI_REn line will not be deasserted between back-to-
back read transfers. The same will happen for non-multiplexed back-to-back write transactions with
WRSETUP and WRHOLD both programmed to 0. In case that NOIDLE/NOIDLEn is 1 and a read is
immediately followed by a write on the EBI_AD lines, one bus turn-around cycle called RDHOLDX is
automatically inserted in between the read and the write action. During a RDHOLDX cycle the external
EBI signals are driven in the same way as during regular RDHOLD cycles, i.e. the EBI_REn line will get
deasserted while the EBI_CSn line will stay asserted.
An IDLE cycle will automatically get inserted for the following cases:
• Between two external device transactions in case the NOIDLE/NOIDLEn bit is 0.
• Between two external device transactions to different banks.
• When no request for an external transaction is available in the EBI.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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