EFM32WG Datasheet, PDF (376/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
14:11
10:0
Name
Reset
Access Description
EPNUM
0x0
RW
Endpoint Number
Indicates the endpoint number on the device serving as the data source or sink.
MPS
0x000
RW
Maximum Packet Size
Indicates the maximum packet size of the associated endpoint.
15.6.36 USB_HCx_INT - Host Channel x Interrupt Register
This register indicates the status of a channel with respect to USB- and AHB-related events. The
application must read this register when the Host Channels Interrupt bit of the Core Interrupt register
(USB_GINTSTS.HCHINT) is set. Before the application can read this register, it must first read the Host
All Channels Interrupt (USB_HAINT) register to get the exact channel number for the Host Channel x
Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding
bits in the USB_HAINT and USB_GINTSTS registers.
Offset
0x3C508
Reset
Access
Bit Position
Name
Bit
31:11
10
9
8
7
6
5
4
3
2
1
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
DATATGLERR
0
RW1
Data Toggle Error
This bit can be set only by the core and the application should write 1 to clear it.
FRMOVRUN
0
RW1
Frame Overrun
This bit can be set only by the core and the application should write 1 to clear it.
BBLERR
0
RW1
Babble Error
This bit can be set only by the core and the application should write 1 to clear it.
XACTERR
0
RW1
Transaction Error
Indicates one of the following errors occurred on the USB: CRC check failure, Timeout, Bit stuff error or False EOP. This bit can be
set only by the core and the application should write 1 to clear it.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
ACK
0
RW1
ACK Response Received/Transmitted Interrupt
This bit can be set only by the core and the application should write 1 to clear it.
NAK
0
RW1
NAK Response Received Interrupt
This bit can be set only by the core and the application should write 1 to clear it.
STALL
0
RW1
STALL Response Received Interrupt
This bit can be set only by the core and the application should write 1 to clear it.
AHBERR
0
RW1
AHB Error
This is generated only in DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding
channel's DMA address register to get the error address.
CHHLTD
0
RW1
Channel Halted
In DMA mode this bit indicates the transfer completed abnormally either because of any USB transaction error or in response to
disable request by the application or because of a completed transfer.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
376
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