EFM32WG Datasheet, PDF (710/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

29.4 Register Map
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The offset register address is relative to the registers base address.
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x054
0x058
0x05C
0x060
0x064
Name
DACn_CTRL
DACn_STATUS
DACn_CH0CTRL
DACn_CH1CTRL
DACn_IEN
DACn_IF
DACn_IFS
DACn_IFC
DACn_CH0DATA
DACn_CH1DATA
DACn_COMBDATA
DACn_CAL
DACn_BIASPROG
DACn_OPACTRL
DACn_OPAOFFSET
DACn_OPA0MUX
DACn_OPA1MUX
DACn_OPA2MUX
Type
RW
R
RW
RW
RW
R
W1
W1
RW
RW
W
RW
RW
RW
RW
RW
RW
RW
Description
Control Register
Status Register
Channel 0 Control Register
Channel 1 Control Register
Interrupt Enable Register
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
Channel 0 Data Register
Channel 1 Data Register
Combined Data Register
Calibration Register
Bias Programming Register
Operational Amplifier Control Register
Operational Amplifier Offset Register
Operational Amplifier Mux Configuration Register
Operational Amplifier Mux Configuration Register
Operational Amplifier Mux Configuration Register
29.5 Register Description
29.5.1 DACn_CTRL - Control Register
Offset
0x000
Reset
Access
Bit Position
Name
Bit
31:22
21:20
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
REFRSEL
0x0
RW
Refresh Interval Select
Select refresh counter timeout value. A channel x will be refreshed with the interval set in this register if the REFREN bit in
DACn_CHxCTRL is set.
Value
0
1
2
Mode
8CYCLES
16CYCLES
32CYCLES
Description
All channels with enabled refresh are refreshed every 8 prescaled cycles
All channels with enabled refresh are refreshed every 16 prescaled cycles
All channels with enabled refresh are refreshed every 32 prescaled cycles
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
710
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