EFM32WG Datasheet, PDF (440/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
Set on each clock low timeout. The timeout value can be set in CLTO bit field in the I2Cn_CTRL register.
14
BITO
0
R
Bus Idle Timeout Interrupt Flag
Set on each bus idle timeout. The timeout value can be set in the BITO bit field in the I2Cn_CTRL register.
13
RXUF
0
R
Receive Buffer Underflow Interrupt Flag
Set when data is read from the receive buffer through the I2Cn_RXDATA register while the receive buffer is empty.
12
TXOF
0
R
Transmit Buffer Overflow Interrupt Flag
Set when data is written to the transmit buffer while the transmit buffer is full.
11
BUSHOLD
0
R
Set when the bus becomes held by the I²C module.
Bus Held Interrupt Flag
10
BUSERR
0
R
Bus Error Interrupt Flag
Set when a bus error is detected. The bus error is resolved automatically, but the current transfer is aborted.
9
ARBLOST
0
R
Arbitration Lost Interrupt Flag
Set when arbitration is lost.
8
MSTOP
0
R
Master STOP Condition Interrupt Flag
Set when a STOP condition has been successfully transmitted. If arbitration is lost during the transmission of the STOP condition,
then the MSTOP interrupt flag is not set.
7
NACK
0
R
Not Acknowledge Received Interrupt Flag
Set when a NACK has been received.
6
ACK
0
R
Acknowledge Received Interrupt Flag
Set when an ACK has been received.
5
RXDATAV
0
R
Receive Data Valid Interrupt Flag
Set when data is available in the receive buffer. Cleared automatically when the receive buffer is read.
4
TXBL
1
R
Transmit Buffer Level Interrupt Flag
Set when the transmit buffer becomes empty. Cleared automatically when new data is written to the transmit buffer.
3
TXC
0
R
Transfer Completed Interrupt Flag
Set when the transmit shift register becomes empty and there is no more data in the transmit buffer.
2
ADDR
0
R
Address Interrupt Flag
Set when incoming address is accepted, i.e. own address or general call address is received.
1
RSTART
0
R
Repeated START condition Interrupt Flag
Set when a repeated start condition is detected.
0
START
0
R
START condition Interrupt Flag
Set when a start condition is successfully transmitted.
16.5.12 I2Cn_IFS - Interrupt Flag Set Register
Offset
0x02C
Reset
Access
Bit Position
Name
Bit
31:17
Name
Reserved
Reset
Access Description
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
440
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