EFM32WG Datasheet, PDF (103/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
Set if the Backup BOD sensing on unregulated power triggers. Must be cleared by software. Please see Section 10.3.4.2 (p. 112)
for details on how to interpret this bit.
12
BUBODBUVIN
0
R
Backup Brown Out Detector, BU_VIN
Set if the Backup BOD sensing on BU_VIN triggers. Must be cleared by software. Please see Section 10.3.4.2 (p. 112) for details
on how to interpret this bit.
11
BUBODVDDDREG
0
R
Backup Brown Out Detector, VDD_DREG
Set if the Backup BOD sensing on VDDD_REG triggers. Must be cleared by software. Please see Section 10.3.4.2 (p. 112) for
details on how to interpret this bit.
10
BODAVDD1
0
R
AVDD1 Bod Reset
Set if analog power domain 1 brown out detector reset has been performed. Must be cleared by software. Please see Table 9.1 (p.
100) for details on how to interpret this bit.
9
BODAVDD0
0
R
AVDD0 Bod Reset
Set if analog power domain 0 brown out detector reset has been performed. Must be cleared by software. Please see Table 9.1 (p.
100) for details on how to interpret this bit.
8
EM4WURST
0
R
EM4 Wake-up Reset
Set if the system has been woken up from EM4 from a reset request from pin. Must be cleared by software. Please see Table 9.1 (p.
100) for details on how to interpret this bit.
7
EM4RST
0
R
EM4 Reset
Set if the system has been in EM4. Must be cleared by software. Please see Table 9.1 (p. 100) for details on how to interpret this bit.
6
SYSREQRST
0
R
System Request Reset
Set if a system request reset has been performed. Must be cleared by software. Please see Table 9.1 (p. 100) for details on how
to interpret this bit.
5
LOCKUPRST
0
R
LOCKUP Reset
Set if a LOCKUP reset has been requested. Must be cleared by software. Please see Table 9.1 (p. 100) for details on how to
interpret this bit.
4
WDOGRST
0
R
Watchdog Reset
Set if a watchdog reset has been performed. Must be cleared by software. Please see Table 9.1 (p. 100) for details on how to
interpret this bit.
3
EXTRST
0
R
External Pin Reset
Set if an external pin reset has been performed. Must be cleared by software. Please see Table 9.1 (p. 100) for details on how
to interpret this bit.
2
BODREGRST
0
R
Brown Out Detector Regulated Domain Reset
Set if a regulated domain brown out detector reset has been performed. Must be cleared by software. Please see Table 9.1 (p. 100)
for details on how to interpret this bit.
1
BODUNREGRST
0
R
Brown Out Detector Unregulated Domain Reset
Set if a unregulated domain brown out detector reset has been performed. Must be cleared by software. Please see Table 9.1 (p.
100) for details on how to interpret this bit.
0
PORST
0
R
Power On Reset
Set if a power on reset has been performed. Must be cleared by software. Please see Table 9.1 (p. 100) for details on how to
interpret this bit.
9.5.3 RMU_CMD - Command Register
Offset
0x008
Reset
Access
Bit Position
Name
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
103
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