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Figure 17.4. USART Receive Buffer Operation
Peripheral Bus
RXDOUBLE
RXDOUBLEX
RXDOUBLEXP
RX buffer elem ent 0
St at us
RXDATA,
RXDATAX,
RXDATAXP
RX buffer elem ent 1
St at us
Shift regist er
St at us
The receive buffer, including the receive shift register can be cleared by setting CLEARRX in
USARTn_CMD. Any frame currently being received will not be discarded.
17.3.2.4.2 Blocking Incoming Data
When using hardware frame recognition, as detailed in Section 17.3.2.8 (p. 458) and
Section 17.3.2.9 (p. 459) , it is necessary to be able to let the receiver sample incoming frames without
passing the frames to software by loading them into the receive buffer. This is accomplished by blocking
incoming data.
Incoming data is blocked as long as RXBLOCK in USARTn_STATUS is set. When blocked, frames
received by the receiver will not be loaded into the receive buffer, and software is not notified by the
RXDATAV flag in USARTn_STATUS or the RXDATAV interrupt flag in USARTn_IF at their arrival. For
data to be loaded into the receive buffer, RXBLOCK must be cleared in the instant a frame is fully
received by the receiver. RXBLOCK is set by setting RXBLOCKEN in USARTn_CMD and disabled by
setting RXBLOCKDIS also in USARTn_CMD. There is one exception where data is loaded into the
receive buffer even when RXBLOCK is set. This is when an address frame is received when operating
in multi-processor mode. See Section 17.3.2.8 (p. 458) for more information.
Frames received containing framing or parity errors will not result in the FERR and PERR interrupt
flags in USARTn_IF being set while RXBLOCK in USARTn_STATUS is set. Hardware recognition is not
applied to these erroneous frames, and they are silently discarded.
Note
If a frame is received while RXBLOCK in USARTn_STATUS is cleared, but stays in the
receive shift register because the receive buffer is full, the received frame will be loaded into
the receive buffer when space becomes available even if RXBLOCK is set at that time.
The overflow interrupt flag RXOF in USARTn_IF will be set if a frame in the receive shift
register, waiting to be loaded into the receive buffer is overwritten by an incoming frame
even though RXBLOCK in USARTn_STATUS is set.
17.3.2.4.3 Clock Recovery and Filtering
The receiver samples the incoming signal at a rate 16, 8, 6 or 4 times higher than the given baud rate,
depending on the oversampling mode given by OVS in USARTn_CTRL. Lower oversampling rates make
higher baud rates possible, but give less room for errors.
When a high-to-low transition is registered on the input while the receiver is idle, this is recognized as a
start-bit, and the baud rate generator is synchronized with the incoming frame.
For oversampling modes 16, 8 and 6, every bit in the incoming frame is sampled three times to gain
a level of noise immunity. These samples are aimed at the middle of the bit-periods, as visualized in
Figure 17.5 (p. 454) . With OVS=0 in USARTn_CTRL, the start and data bits are thus sampled at
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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