LAN9353 Datasheet, PDF (99/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.2.3 100BASE-TX RECEIVE
The 100BASE-TX receive data path is shown in Figure 9-3. Shaded blocks are those which are internal to the PHY.
Each major block is explained in the following sections.
FIGURE 9-3:
100BASE-TX RECEIVE DATA PATH
Port x
MAC
Internal
MII Receive Clock
100M
PLL
Internal
MII MAC
MII 25MHz by 4 bits _Interface
NRZI
Converter
NRZI
MLT-3
Converter
25MHz
by 4 bits
4B/5B
Decoder
25MHz by
5 bits
125 Mbps Serial
MLT-3
DSP: Timing
recovery, Equalizer
and BLW Correction
Descrambler
and SIPO
A/D
Converter
MLT-3
Magnetics
MLT-3
RJ45
MLT-3 CAT-5
6 bit Data
9.2.3.1 100M Receive Input
The MLT-3 data from the cable is fed into the PHY on inputs RXPx and RXNx via a 1:1 ratio transformer. The ADC sam-
ples the incoming differential signal at a rate of 125M samples per second. Using a 64-level quantizer, 6 digital bits are
generated to represent each sample. The DSP adjusts the gain of the ADC according to the observed signal levels such
that the full dynamic range of the ADC can be used.
9.2.3.2 Equalizer, BLW Correction and Clock/Data Recovery
The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates for phase and ampli-
tude distortion caused by the physical channel consisting of magnetics, connectors, and CAT- 5 cable. The equalizer
can restore the signal for any good-quality CAT-5 cable between 1m and 100m.
If the DC content of the signal is such that the low-frequency components fall below the low frequency pole of the iso-
lation transformer, then the droop characteristics of the transformer will become significant and Baseline Wander (BLW)
on the received signal will result. To prevent corruption of the received data, the PHY corrects for BLW and can receive
the ANSI X3.263-1995 FDDI TP-PMD defined “killer packet” with no bit errors.
The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing unit of the DSP,
selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to
extract the serial data from the received signal.
9.2.3.3 NRZI and MLT-3 Decoding
The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an
NRZI data stream.
9.2.3.4 Descrambler
The descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel
Out (SIPO) conversion of the data.
 2015 Microchip Technology Inc.
DS00001925A-page 99