LAN9353 Datasheet, PDF (47/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
5.2 Special Restrictions on Back-to-Back Cycles
5.2.1 BACK-TO-BACK WRITE-READ CYCLES
It is important to note that there are specific restrictions on the timing of back-to-back host write-read operations. These
restrictions concern reading registers after any write cycle that may affect the register. In all cases there is a delay
between writing to a register and the new value becoming available to be read. In other cases, there is a delay between
writing to a register and the subsequent side effect on other registers.
In order to prevent the host from reading stale data after a write operation, minimum wait periods have been established.
These periods are specified in Table 5-2. The host processor is required to wait the specified period of time after writing
to the indicated register before reading the resource specified in the table. Note that the required wait period is depen-
dent upon the register being read after the write.
Performing “dummy” reads of the Byte Order Test Register (BYTE_TEST) register is a convenient way to guarantee that
the minimum write-to-read timing restriction is met. Table 5-2 shows the number of dummy reads that are required
before reading the register indicated. The number of BYTE_TEST reads in this table is based on the minimum cycle
timing of 45ns. For microprocessors with slower busses the number of reads may be reduced as long as the total time
is equal to, or greater than the time specified in the table. Note that dummy reads of the BYTE_TEST register are not
required as long as the minimum time period is met.
Note that depending on the host interface mode in use, the basic host interface cycle may naturally provide sufficient
time between writes and read. It is required of the system design and register access mechanisms to ensure the proper
timing. For example, a write and read to the same register may occur faster than a write and read to different registers.
TABLE 5-2: READ AFTER WRITE TIMING RULES
After Writing...
any register
Interrupt Configuration Regis-
ter (IRQ_CFG)
Interrupt Enable Register
(INT_EN)
Interrupt Status Register
(INT_STS)
Power Management Control
Register (PMT_CTRL)
wait for this many
nanoseconds...
45
60
90
60
180
170
165
170
160
or Perform this many
Reads of BYTE_TEST…
(assuming T_cyc of 45ns)
1
2
2
2
4
4
4
4
4
before reading...
the same register
or any other register affected
by the write
Interrupt Configuration Regis-
ter (IRQ_CFG)
Interrupt Configuration Regis-
ter (IRQ_CFG)
Interrupt Status Register
(INT_STS)
Interrupt Configuration Regis-
ter (IRQ_CFG)
Interrupt Status Register
(INT_STS)
Power Management Control
Register (PMT_CTRL)
Interrupt Configuration Regis-
ter (IRQ_CFG)
Interrupt Status Register
(INT_STS)
 2015 Microchip Technology Inc.
DS00001925A-page 47