LAN9353 Datasheet, PDF (138/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.2.20.12 PHY x EDPD NLP / Crossover Time / EEE Configuration Register (PHY_EDPD_CFG_x)
Index (decimal): 16
Size:
16 bits
This register is used to Enable EEE functionality and control NLP pulse generation and the Auto-MDIX Crossover Time
of the PHY.
Bits
Description
Type
15 EDPD TX NLP Enable
R/W
Enables the generation of a Normal Link Pulse (NLP) with a selectable inter- _NASR
val while in Energy Detect Power-Down. 0=disabled, 1=enabled.
Note 14
The Energy Detect Power-Down (EDPWRDOWN) bit in the PHY x Mode
Control/Status Register (PHY_MODE_CONTROL_STATUS_x) needs to be
set in order to enter Energy Detect Power-Down mode and the PHY needs to
be in the Energy Detect Power-Down state in order for this bit to generate the
NLP.
14:13
The EDPD TX NLP Independent Mode bit of this register also needs to be set
when setting this bit.
EDPD TX NLP Interval Timer Select
Specifies how often a NLP is transmitted while in the Energy Detect Power-
Down state.
R/W
NASR
Note 14
00b: 1 s
01b: 768 ms
10b: 512 ms
11b: 256 ms
12 EDPD RX Single NLP Wake Enable
R/W
When set, the PHY will wake upon the reception of a single Normal Link
NASR
Pulse. When clear, the PHY requires two link pluses, within the interval spec- _{Note 14}
ified below, in order to wake up.
11:10
Single NLP Wake Mode is recommended when connecting to “Green” net-
work devices.
EDPD RX NLP Max Interval Detect Select
These bits specify the maximum time between two consecutive Normal Link
Pulses in order for them to be considered a valid wake up signal.
R/W
NASR
Note 14
00b: 64 ms
01b: 256 ms
10b: 512 ms
11b: 1 s
9:4 RESERVED
RO
3
EDPD TX NLP Independent Mode
R/W
When set, each PHY port independently detects power down for purposes of _NASR
the EDPD TX NLP function (via the EDPD TX NLP Enable bit of this register). _{Note 14}
When cleared, both ports need to be in a power-down state in order to gener-
ate TX NLPs during energy detect power-down.
Normally set this bit when setting EDPD TX NLP Enable.
Default
0b
00b
0b
00b
-
0b
DS00001925A-page 138
 2015 Microchip Technology Inc.