LAN9353 Datasheet, PDF (19/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 3-5: LAN PORT A & B POWER AND COMMON PIN DESCRIPTIONS
Num
Pins
Name
Symbol
Buffer
Type
Description
Used for internal bias circuits. Connect to an exter-
nal 12.1 kΩ, 1% resistor to ground.
1 Bias Reference
RBIAS
Refer to the device reference schematic for connec-
AI
tion information.
Note:
The nominal voltage is 1.2 V and the
resistor will dissipate approximately
1 mW of power.
Port A and B FX-LOS Enable. This 3 level strap
input selects between FX-LOS and FX-SD / copper
twisted pair mode.
Port A and B
1 FX-LOS Enable
Strap
FXLOSEN
A level below 1 V (typ.) selects FX-SD / copper
twisted pair for ports A and B, further determined by
AI
FXSDENA and FXSDENB.
A level of 1.5 V selects FX-LOS for port A and FX-
SD / copper twisted pair for port B, further deter-
mined by FXSDENB.
+3.3 V Port A
1 Analog Power
Supply
+3.3 V Port B
1 Analog Power
Supply
+3.3 V Master
1
Bias Power
Supply
Port A
1
Transmitter
+1.2 V Power
Supply
VDD33TXRX1
VDD33TXRX2
VDD33BIAS
VDD12TX1
A level above 2 V (typ.) selects FX-LOS for ports A
and B.
See Note 5.
P
See Note 5.
P
See Note 5.
P
This pin is supplied from either an external 1.2 V
supply or from the device’s internal regulator via the
P
PCB. This pin must be tied to the VDD12TX2 pin for
proper operation.
See Note 5.
Port B
1
Transmitter
+1.2 V Power
Supply
VDD12TX2
This pin is supplied from either an external 1.2 V
supply or from the device’s internal regulator via the
P
PCB. This pin must be tied to the VDD12TX1 pin for
proper operation.
See Note 5.
Note 5: Refer to Section 4.0, "Power Connections," on page 38, the device reference schematics, and the device
LANCheck schematic checklist for additional connection information.
 2015 Microchip Technology Inc.
DS00001925A-page 19