LAN9353 Datasheet, PDF (425/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
15.8.4 1588 INTERRUPT ENABLE REGISTER (1588_INT_EN)
Offset:
Bank:
10Ch
na
Size:
32 bits
This read/write register contains the 1588 interrupt enable bits.
If enabled, these interrupt bits are cascaded into the 1588 Interrupt Event (1588_EVNT) bit of the Interrupt Status Reg-
ister (INT_STS). Writing a 1 to an interrupt enable bits will enable the corresponding interrupt as a source. Status bits
will still reflect the status of the interrupt source regardless of whether the source is enabled as an interrupt in this reg-
ister. The 1588 Interrupt Event Enable (1588_EVNT_EN) bit of the Interrupt Enable Register (INT_EN) must also be set
in order for an actual system level interrupt to occur. Refer to Section 8.0, "System Interrupts," on page 84 for additional
information.
Bits
Description
31:24
23:16
15
1588 GPIO Falling Edge Interrupt Enable (1588_GPIO_FE_EN[7:0])
1588 GPIO Rising Edge Interrupt Enable (1588_GPIO_RE_EN[7:0])
RESERVED
14:12 1588 TX Timestamp Enable (1588_TX_TS_EN[2:0])
11 RESERVED
10:8 1588 RX Timestamp Enable (1588_RX_TS_EN[2:0])
7:2 RESERVED
1
1588 Timer B Interrupt Enable (1588_TIMER_EN_B)
0
1588 Timer A Interrupt Enable (1588_TIMER_EN_A)
Type
R/W
R/W
RO
R/W
RO
R/W
RO
R/W
R/W
Default
00h
00h
-
000b
-
000b
-
0b
0b
 2015 Microchip Technology Inc.
DS00001925A-page 425