LAN9353 Datasheet, PDF (392/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
14.4.1.6 Port 0 PHY Mode I²C Managed
In this mode, Physical PHYs A and B are accessed via the PMI. Virtual PHY 0 is accessed via an external master
attached to the Port 0 MII pins. The PMI parallel interface is accessible via the I²C slave and the EEPROM Loader. The
EEPROM Loader may access PHYs A and B through the PMI registers. The Virtual PHY 0 parallel interface is acces-
sible via the I²C slave and the EEPROM Loader.
Figure 14-8 details the MII Mode Multiplexer management path connections for this mode.
FIGURE 14-8:
MII MUX MANAGEMENT PATH CONNECTIONS - PHY MODE I²C MANAGED
mdi SMI Slave
mdo
mdc
Parallel
Master
mdio_dir
mdi Virtual PHY 0
mdo
mdc
Parallel
Slave
mdio_dir
mdi PHY B
mdo
mdio_dir
mdc
mdi PHY A
mdo
mdio_dir
mdc
Management
Mode Selection
default =
1
MII Pins
mdio_dir
p
mdo
i
n
mdi
m
mdc_dir
u
x
mdc_out
i
n
mdc_in
g
P0_MDIO
P0_MDC
Management
Mode Selection
mdo mdc mdi mdio_en_n
PMI
Parallel Slave
DS00001925A-page 392
 2015 Microchip Technology Inc.