LAN9353 Datasheet, PDF (397/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
• Forwarding or filtering PTP packets as needed to support ordinary, boundary or transparent clock mode
• Recording the timestamp of transmitted packets into registers
- Accounting for the egress latency
• Updating the correction field to account for the residence time in the switch and updating the layer 3 checksum
and layer 2 FCS
- Accounting for the peer delay and link asymmetry
• One-step on-the-fly timestamp insertion for Sync packets and updating the layer 3 checksum and layer 2 FCS
• One-step on-the-fly turnaround time insertion for Pdelay_Req packets and updating the layer 3 checksum and
layer 2 FCS
Note: Support for the IEEE 1588-2002 (v1) packet format is not provided.
Three instances of this sub-module are used, one for each switch port. When a switch port is connected to an SoC MAC,
the PTP sub-module for that switch port typically would not be configured to operate.
15.2.1 RECEIVE FRAME PROCESSING
15.2.1.1 Ingress Time Snapshot
For each Ethernet frame, the receive frame processing detects the SFD field of the frame and temporarily saves the
current 1588 Clock value.
INGRESS LATENCY
The ingress latency is the amount of time between the start of the frame’s first symbol after the SFD on the network
medium and the point when the 1588 clock value is internally captured. It is specified by the RX Latency (RX_LA-
TENCY[15:0]) field in the 1588 Port x Latency Register (1588_LATENCY_x) and is subtracted from the 1588 Clock
value at the detection of the SFD. The setting is used to adjust the internally captured 1588 clock value such that the
resultant timestamp more accurately corresponds to the start of the frame’s first symbol after the SFD on the network
medium.
The ingress latency consists of the receive latency of the PHY, whether internal or external and the latency of the 1588
frame detection circuitry. The value depends on the port mode. Typical values are:
• 100BASE-TX: 285ns
• 100BASE-FX: 231ns plus the receive latency of the fiber transceiver
• 10BASE-T: 1674ns
• 100Mbps MII: 20ns plus any external receive latency
• 10Mbps MII: 20ns plus any external receive latency
• 200Mbps TMII: 20ns plus any external receive latency
• 100Mbps RMII: 70ns plus any external receive latency
• 10Mbps RMII: 440ns plus any external receive latency
15.2.1.2 1588 Receive Parsing
The 1588 Receive parsing block parses the incoming frame to identify 1588 PTP messages.
Note: Support for the IEEE 1588-2002 (v1) packet format is not provided.
The Receive parsing block may be programmed to detect PTP messages encoded in UDP/IPv4, UDP/IPv6 and Layer
2 Ethernet formats via the RX IPv4 Enable (RX_IPV4_EN), RX IPv6 Enable (RX_IPV6_EN) and RX Layer 2 Enable
(RX_LAYER2_EN) bits in the 1588 Port x RX Parsing Configuration Register (1588_RX_PARSE_CONFIG_x).
VLAN tagged and non-VLAN tagged frame formats are supported. Multiple VLAN tags are handled as long as they all
use the standard type of 0x8100. Both Ethernet II (type field) and 802.3 (length field) w/ SNAP frame formats are sup-
ported.
The following tests are made to determine that the packet is a PTP message.
• MAC Destination Address checking is enabled via the RX MAC Address Enable (RX_MAC_ADDR_EN) in the
1588 Port x RX Parsing Configuration Register (1588_RX_PARSE_CONFIG_x).
For the Layer 2 message format, the addresses of 01:1B:19:00:00:00 or 01:80:C2:00:00:0E may be enabled via
the 1588 Port x RX Parsing Configuration Register (1588_RX_PARSE_CONFIG_x). Either address is allowed for
Peer delay and non-Peer delay messages.
 2015 Microchip Technology Inc.
DS00001925A-page 397