LAN9353 Datasheet, PDF (246/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
10.7 Switch Fabric Control and Status Registers
This section details the various indirectly addressable switch control and status registers that reside within the Switch
Fabric. The switch control and status registers allow configuration of each individual switch port, the Switch Engine and
Buffer Manager. Switch Fabric related interrupts and resets are also controlled and monitored via the switch CSRs.
The switch CSRs are not directly mapped into the system address space. All switch CSRs are accessed indirectly via
the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD), the Switch Fabric CSR Interface Data
Register (SWITCH_CSR_DATA) and the Switch Fabric CSR Interface Direct Data Registers (SWITCH_CSR_DI-
RECT_DATA) in the system CSR address space. All accesses to the switch CSRs must be performed through these
registers. Refer to Section 10.6, "Switch Fabric Interface Logic Registers" for additional information.
Note:
The flow control settings of the switch ports are configured via the Switch Fabric Interface Logic Registers:
Port 1 Manual Flow Control Register (MANUAL_FC_1), Port 2 Manual Flow Control Register (MANUAL_F-
C_2) and Port 0 Manual Flow Control Register (MANUAL_FC_0) located in the system CSR address space.
Table 10-9 lists the Switch CSRs and their corresponding addresses in order. The Switch Fabric registers can be cate-
gorized into the following sub-sections:
• Section 10.7.1, "General Switch CSRs," on page 255
• Section 10.7.2, "Switch Port 0, Port 1 and Port 2 CSRs," on page 259
• Section 10.7.3, "Switch Engine CSRs," on page 286
• Section 10.7.4, "Buffer Manager CSRs," on page 323
TABLE 10-9: INDIRECTLY ACCESSIBLE SWITCH CONTROL AND STATUS REGISTERS
Address
(INDIRECT)
Register Name (SYMBOL)
0000h
0001h
0002h-0003h
0004h
0005h
0006h-03FFh
General Switch CSRs
Switch Device ID Register (SW_DEV_ID)
Switch Reset Register (SW_RESET)
Reserved for Future Use (RESERVED)
Switch Global Interrupt Mask Register (SW_IMR)
Switch Global Interrupt Pending Register (SW_IPR)
Reserved for Future Use (RESERVED)
0400h
0401h
0402h-040Fh
0410h
0411h
0412h
0413h
0414h
0415h
0416h
0417h
Switch Port 0 CSRs (x=0)
Port x MAC Version ID Register (MAC_VER_ID_x)
Port x MAC Receive Configuration Register (MAC_RX_CFG_x)
Reserved for Future Use (RESERVED)
Port x MAC Receive Undersize Count Register (MAC_RX_UNDSZE_CNT_x)
Port x MAC Receive 64 Byte Count Register (MAC_RX_64_CNT_x)
Port x MAC Receive 65 to 127 Byte Count Register (MAC_RX_65_TO_127_CNT_x)
Port x MAC Receive 128 to 255 Byte Count Register (MAC_RX_128_TO_255_CNT_x)
Port x MAC Receive 256 to 511 Byte Count Register (MAC_RX_256_TO_511_CNT_x)
Port x MAC Receive 512 to 1023 Byte Count Register (MAC_RX_512_TO_1023_CNT_x)
Port x MAC Receive 1024 to Max Byte Count Register (MAC_RX_1024_TO_MAX_CNT_x)
Port x MAC Receive Oversize Count Register (MAC_RX_OVRSZE_CNT_x)
DS00001925A-page 246
 2015 Microchip Technology Inc.