LAN9353 Datasheet, PDF (172/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.2.20.38 PHY x EEE Advertisement Register (PHY_EEE_ADV_x)
Index (In Decimal): 7.60
Size:
16 bits
BITS
15:2
1
0
DESCRIPTION
RESERVED
100BASE-TX EEE
0 = Do not advertise EEE capability for 100BASE-TX.
1 = Advertise EEE capability for 100BASE-TX.
RESERVED
TYPE
RO
Note 33
DEFAULT
-
Note 34
RO
-
Note 33: This bit is read/write (R/W). However, the user must not set this bit if EEE is disabled.
Note 34: The default value of this field is determined by the value of the PHY Energy Efficient Ethernet Enable (PHY-
EEEEN) of the PHY x EDPD NLP / Crossover Time / EEE Configuration Register (PHY_EDPD_CFG_x) on
page 138. If PHY Energy Efficient Ethernet Enable (PHYEEEEN) is 0b, this field is 0b and 100BASE-TX
EEE capability is not advertised. If PHY Energy Efficient Ethernet Enable (PHYEEEEN) is 1b, then this field
is 1b and 100BASE-TX EEE capability is advertised.
DS00001925A-page 172
 2015 Microchip Technology Inc.