LAN9353 Datasheet, PDF (162/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
9.2.20.29 PHY x Wakeup Control and Status Register (PHY_WUCSR_x)
Index (In Decimal): 3.32784
Size:
16 bits
Bits
Description
Type
15:9 RESERVED
RO
8
WoL Configured
R/W/
This bit may be set by software after the WoL registers are configured. This
NASR
sticky bit (and all other WoL related register bits) is reset only via a power
Note 26
cycle or a pin reset, allowing software to skip programming of the WoL regis-
ters in response to a WoL event.
Note: Refer to Section 9.2.12, "Wake on LAN (WoL)," on page 109 for
additional information.
7
Perfect DA Frame Received (PFDA_FR)
R/WC/
The MAC sets this bit upon receiving a valid frame with a destination address _NASR
that matches the physical address.
Note 26
6
Remote Wakeup Frame Received (WUFR)
The MAC sets this bit upon receiving a valid remote Wakeup Frame.
R/WC/
NASR
Note 26
5
Magic Packet Received (MPR)
The MAC sets this bit upon receiving a valid Magic Packet.
R/WC/
NASR
Note 26
4
Broadcast Frame Received (BCAST_FR)
The MAC Sets this bit upon receiving a valid broadcast frame.
R/WC/
NASR
Note 26
3
Perfect DA Wakeup Enable (PFDA_EN)
R/W/
When set, remote wakeup mode is enabled and the MAC is capable of wak- _NASR
ing up on receipt of a frame with a destination address that matches the
Note 26
physical address of the device. The physical address is stored in the PHY x
MAC Receive Address A Register (PHY_RX_ADDRA_x), PHY x MAC
Receive Address B Register (PHY_RX_ADDRB_x) and PHY x MAC Receive
Address C Register (PHY_RX_ADDRC_x).
2
Wakeup Frame Enable (WUEN)
When set, remote wakeup mode is enabled and the MAC is capable of
detecting Wakeup Frames as programmed in the Wakeup Filter.
R/W/
NASR
Note 26
1
Magic Packet Enable (MPEN)
When set, Magic Packet wakeup mode is enabled.
R/W/
NASR
Note 26
0
Broadcast Wakeup Enable (BCST_EN)
R/W/
When set, remote wakeup mode is enabled and the MAC is capable of wak- _NASR
ing up from a broadcast frame.
Note 26
Default
-
0b
0b
0b
0b
0b
0b
0b
0b
0b
Note 26: Register bits designated as NASR are reset when the PHY Reset is generated via the Reset Control Reg-
ister (RESET_CTL). The NASR designation is only applicable when the Soft Reset (PHY_SRST) bit of the
PHY x Basic Control Register (PHY_BASIC_CONTROL_x) is set.
DS00001925A-page 162
 2015 Microchip Technology Inc.