LAN9353 Datasheet, PDF (55/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
Virtual PHY reset completion can be determined by polling the VPHY_1_RST bit in the Reset Control Register
(RESET_CTL) or the Reset bit in the Port x Virtual PHY Basic Control Register (VPHY_BASIC_CTRL_x) until it clears.
Under normal conditions, the VPHY_1_RST and Reset bit will clear approximately 1 us after the Virtual PHY reset
occurrence.
Refer to Section 9.3.3, "Virtual PHY Resets," on page 183 for additional information on Virtual PHY resets.
Switch Reset
A reset of the Switch Fabric, including its MACs, is performed by setting the SW_RESET bit in the Switch Reset Register
(SW_RESET). The bit must then be manually cleared.
The registers described in Section 10.7, "Switch Fabric Control and Status Registers," on page 246 are reset. The func-
tionality described in Section 10.5, "Switch Fabric Interface Logic," on page 226 and the registers described in Section
10.6, "Switch Fabric Interface Logic Registers," on page 231 are not reset.
No other modules of the device are affected by this reset.
1588 Reset
A reset of all 1588 related logic, including the clock/event generation and 1588 TSUs, is performed by setting the 1588
Reset (1588_RESET) bit in the 1588 Command and Control Register (1588_CMD_CTL).
The registers described in Section 15.0, "IEEE 1588," on page 394 are reset.
No other modules of the device are affected by this reset.
1588 reset completion can be determined by polling the 1588 Reset (1588_RESET) bit in the 1588 Command and Con-
trol Register (1588_CMD_CTL) until it clears.
 2015 Microchip Technology Inc.
DS00001925A-page 55