LAN9353 Datasheet, PDF (198/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 9-22: EMULATED LINK PARTNER PAUSE FLOW CONTROL ABILITY DEFAULT VALUES
VPHY
Symmetric
Pause
(register 4.10)
VPHY
Asymmetric
Pause
(register 4.11)
FD_FC_strap_x
Link Partner
Symmetric
Pause
(register 5.10)
Link Partner
Asymmetric
Pause
(register 5.11)
No Flow Control
0
0
x
0
0
Enabled
Symmetric Pause
1
0
x
1
0
Asymmetric
0
1
x
1
1
Pause Towards
Switch
Asymmetric
1
1
0
0
1
Pause Towards
MAC
Symmetric Pause
1
1
1
1
1
Note 58: The emulated link partner’s ability is based on the duplex_strap_x and speed_strap_x, as well as on the
Auto-Negotiation success. Table 9-23 defines the default capabilities of the emulated link partner as a func-
tion of these signals. For more information on the Virtual PHY Auto-Negotiation, see Section 9.3.1, "Virtual
PHY Auto-Negotiation," on page 181.
TABLE 9-23: EMULATED LINK PARTNER DEFAULT ADVERTISED ABILITY
duplex_strap_0 (port 0) /
duplex_strap_1 (port 1)
1
1
0
0
speed_strap_0 (port 0) /
speed_strap_1 (port 1)
0
1
0
1
Advertised Link Partner Ability
(Bits 8,7,6,5)
10BASE-T full-duplex (0010)
100BASE-X full-duplex (1000)
10BASE-T half-duplex (0001)
100BASE-X half-duplex (0100)
DS00001925A-page 198
 2015 Microchip Technology Inc.