LAN9353 Datasheet, PDF (407/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
The 1588 Port x TX Delay_Req Egress Time Seconds Register (1588_TX_DREQ_SEC_x) and the 1588 Port x TX
Delay_Req Egress Time NanoSeconds Register (1588_TX_DREQ_NS_x) hold the egress time of the Delay_Req mes-
sage.
These registers are updated by the H/W when the Delay_Req message is transmitted independent of the settings in the
TX PTP Message Type Enable (TX_PTP_MESSAGE_EN[15:0]) bits.
As above (including all applicable notes):
• The versionPTP and domainNumber fields and alternateMasterFlag in the flagField of the PTP header are
checked, if enabled.
Note: Support for the IEEE 1588-2002 (v1) packet format is not provided.
• At the end of the frame, the frame’s FCS and the UDP checksum (for IPv4 and IPv6 formats) are verified, if
enabled.
If all tests pass, then the Delay_Req message information is updated and available for the receive function.
15.2.2.4 Egress Packet Modifications
Modifications to frames on egress are divided into two categories, those to support one-step transparent clock residence
time corrections and those to support one-step operations from the Host software.
Bit 7 of the PTP header’s reserved byte (the byte which is also used to hold the ingress time seconds) is used to indicate
packets that need to have their correction field adjusted for residence time. This bit is set on ingress when the correction
field adjustment process is started.
When bit 7 of the PTP header’s reserved byte is cleared, the alternate function, if any, for the message type is to be
performed, if it is enabled. The Host S/W should normally have bit 7 cleared.
Note: The offset of the reserved byte is specified by the TX PTP 1 Reserved Byte Offset (TX_PTP_1_RSVD_OFF-
SET[5:0]) field in the 1588 Port x TX Modification Register (1588_TX_MOD_x).
Proper operation of the transmitter requires that the reserved byte resides after the versionPTP field and
before the correctionField.
For version 2 of IEEE 1588, the reserved byte at offset 5 should be used.
EGRESS CORRECTION FIELD RESIDENCE TIME ADJUSTMENT
In order to support one-step transparent clock operation, the residence time delay through the device is accounted for
by adjusting the correctionField of certain packets.
This function is enabled per PTP message type via the TX PTP Correction Field Message Type Enable (TX_PT-
P_CF_MSG_EN[15:0]) bits in the 1588 Port x TX Modification Register (1588_TX_MOD_x).
Typically the Sync message is enabled for both end-to-end and peer-to-peer transparent clocks, the Delay_Req, PDe-
lay_Req and PDelay_Resp messages are enabled only for end-to-end transparent clocks.
As described above, messages from the Host S/W would normally have bit 7 of the PTP header’s reserved byte clear
and are not modified in this manner. Typically, bit 7 is only set on ingress when the correction field adjustment process
is started.
Note: The Host S/W should normally keep bit 7 of the PTP header’s reserved byte clear for Sync, Delay_Req,
PDelay_Req and PDelay_Resp messages so that residence time adjustment is not performed.
Following the determination of packet format and qualification of the packet as a PTP message above, the PTP header
is checked.
• The versionPTP field of the PTP header is checked against the TX PTP Version (TX_PTP_VERSION[3:0]) field in
the 1588 Port x TX Timestamp Configuration Register (1588_TX_TIMESTAMP_CONFIG_x). Only those mes-
sages with a matching version will have their correction field modified. A setting of 0 allows any PTP version.
Note: Support for the IEEE 1588-2002 (v1) packet format is not provided.
Note: The domainNumber field and alternateMasterFlag in the flagField of the PTP header are not tested for pur-
pose of correction field modification.
The correctionField is modified as follows:
 2015 Microchip Technology Inc.
DS00001925A-page 407