LAN9353 Datasheet, PDF (404/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
If the FCS and checksum tests pass, the frame is filtered by inserting a receive symbol error and the 1588 Port x RX
Filtered Count Register (1588_RX_FILTERED_CNT_x) is incremented.
Note: The MAC will count this as an errored packet.
Note:
Message filtering is an additional, separately enabled, feature verses any packet ingress time recording and
packet modification. Although these functions typically would not be used together on the same message
type.
15.2.2 TRANSMIT FRAME PROCESSING
15.2.2.1 Egress Time Snapshot
For each Ethernet frame, the transmit frame processing detects the SFD field of the frame and temporarily saves the
current 1588 Clock value.
EGRESS LATENCY
The egress latency is the amount of time between the point when the 1588 clock value is internally captured and the
start of the frame’s first symbol after the SFD on the network medium. It is specified by the TX Latency (TX_LA-
TENCY[15:0]) field in the 1588 Port x Latency Register (1588_LATENCY_x) and is added to the 1588 Clock value at
the detection of the SFD. The setting is used to adjust the internally captured 1588 clock value such that the resultant
timestamp more accurately corresponds to the start of the frame’s first symbol after the SFD on the network medium.
The egress latency consists of the transmit latency of the PHY, whether internal or external and the latency of the 1588
frame detection circuitry. The value depends on the port mode. Typical values are:
• 100BASE-TX: 95ns
• 100BASE-FX: 68ns plus the transmit latency of the fiber transceiver
• 10BASE-T: 1139ns
• 100Mbps MII: 20ns plus any external transmit latency
• 10Mbps MII: 380ns plus any external transmit latency
• 200Mbps TMII: 0ns plus any external transmit latency
• 100Mbps RMII: 20ns plus any external transmit latency
• 10Mbps RMII: 20ns plus any external transmit latency
15.2.2.2 1588 Transmit Parsing
The 1588 Transmit parsing block parses the outgoing frame to identify 1588 PTP messages.
Note: Support for the IEEE 1588-2002 (v1) packet format is not provided.
The Transmit parsing block may be programmed to detect PTP messages encoded in UDP/IPv4, UDP/IPv6 and Layer
2 Ethernet formats via the TX IPv4 Enable (TX_IPV4_EN), TX IPv6 Enable (TX_IPV6_EN) and TX Layer 2 Enable
(TX_LAYER2_EN) bits in the 1588 Port x TX Parsing Configuration Register (1588_TX_PARSE_CONFIG_x).
VLAN tagged and non-VLAN tagged frame formats are supported. Multiple VLAN tags are handled as long as they all
use the standard type of 0x8100. Both Ethernet II (type field) and 802.3 (length field) w/ SNAP frame formats are sup-
ported.
The following tests are made to determine that the packet is a PTP message.
• MAC Destination Address checking is enabled via the TX MAC Address Enable (TX_MAC_ADDR_EN) in the
1588 Port x TX Parsing Configuration Register (1588_TX_PARSE_CONFIG_x).
For the Layer 2 message format, the addresses of 01:1B:19:00:00:00 or 01:80:C2:00:00:0E may be enabled via
the 1588 Port x TX Parsing Configuration Register (1588_TX_PARSE_CONFIG_x). Either address is allowed for
Peer delay and non-Peer delay messages.
For IPv4/UDP messages, any of the IANA assigned multicast IP destination addresses for IEEE 1588
(224.0.1.129 and 224.0.1.130 through .132), as well as the IP destination address for the Peer Delay Mechanism
(224.0.0.107) may be enabled via the 1588 Port x TX Parsing Configuration Register (1588_TX_PARSE_CON-
FIG_x). These IP addresses map to the 802.3 MAC addresses of 01:00:5e:00:01:81 through 01:00:5e:00:01:84
and 01:00:5e:00:00:6B. Any of these addresses are allowed for Peer delay and non-Peer delay messages.
For IPv6/UDP messages, any of the IANA assigned multicast IP destination addresses for IEEE 1588
(FF0X:0:0:0:0:0:0:181 and FF0X:0:0:0:0:0:0:182 through :184), as well as the IP destination address for the Peer
Delay Mechanism (FF02:0:0:0:0:0:0:6B) may be enabled via the 1588 Port x TX Parsing Configuration Register
DS00001925A-page 404
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