LAN9353 Datasheet, PDF (82/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 7-2: HARD-STRAP CONFIGURATION STRAP DEFINITIONS (CONTINUED)
Strap Name
P1_clock_strength_strap
Description
Pins
Switch Port 1 Clock Strength Strap: Configures the default
value of the RMII/Turbo MII Clock Strength bit in the (x=1)
Port x Virtual PHY Special Control/Status Register
(VPHY_SPECIAL_CONTROL_STATUS_x).
P1_MODE0
turbo_mii_enable_strap_1
0 = 12ma
1 = 16ma
See Table 7-4 for the combined Port 1 mode strapping.
Switch Port 1 Turbo MII Enable Strap: Configures the
default value of the Turbo Mode Enable bit in the (x=1) Port
x Virtual PHY Special Control/Status Register (VPHY_SPE-
CIAL_CONTROL_STATUS_x) when in MII PHY mode.
P1_MODE1
phy_addr_sel_strap
fx_mode_strap_1
0 = 100Mbps
1 = 200Mbps
See Table 7-4 for the combined Port 1 mode strapping.
Switch PHY Address Select Strap: Configures the default
MII management address values for the PHYs and Virtual
PHY as detailed in Section 9.1.1, "PHY Addressing," on
page 94.
PHY A FX Mode Strap: Selects FX mode for PHY A.
This strap is set high when FXLOSEN is above 1 V (typ.) or
FXSDENA is above 1 V (typ.).
PHYADD
FXLOSEN :
FXSDENA
fx_mode_strap_2
PHY B FX Mode Strap: Selects FX mode for PHY B.
This strap is set high when FXLOSEN is above 2 V (typ.) or
FXSDENB is above 1 V (typ.).
FXLOSEN :
FXSDENB
fx_los_strap_1
PHY A FX-LOS Select Strap: Selects Loss of Signal mode FXLOSEN
for PHY A.
This strap is set high when FXLOSEN is above 1 V (typ.).
fx_los_strap_2
PHY B FX-LOS Select Strap: Selects Loss of Signal mode FXLOSEN
for PHY B.
This strap is set high when FXLOSEN is above 2 V (typ.).
DS00001925A-page 82
 2015 Microchip Technology Inc.