LAN9353 Datasheet, PDF (36/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
TABLE 3-11: MISCELLANEOUS PIN DESCRIPTIONS
Num
Pins
Name
1 Interrupt Output
1
System Reset
Input
Symbol
IRQ
RST#
Buffer
Type
Description
Interrupt request output. The polarity, source and
buffer type of this signal is programmable via the
VO8/VOD8 Interrupt Configuration Register (IRQ_CFG). For
more information, refer to Section 8.0, "System
Interrupts," on page 84.
VIS
(PU)
As an input, this active low signal allows external
hardware to reset the device. The device also con-
tains an internal power-on reset circuit. Thus this
signal may be left unconnected if an external hard-
ware reset is not needed. When used this signal
must adhere to the reset timing requirements as
detailed in the Section 20.0, "Operational Character-
istics," on page 502.
1
Regulator
Enable
1
Test Mode
1
Crystal Input
1 Crystal Output
1
Crystal +1.2 V
Power Supply
1 Crystal Ground
1
Reserved
REG_EN
TESTMODE
OSCI
OSCO
OSCVDD12
OSCVSS
RESERVED
AI
VIS
(PD)
ICLK
OCLK
P
P
-
When tied to 3.3 V, the internal 1.2 V regulators are
enabled.
This pin must be tied to VSS for proper operation.
External 25 MHz crystal input. This signal can also
be driven by a single-ended clock oscillator. When
this method is used, OSCO should be left uncon-
nected.
External 25 MHz crystal output.
Supplied by the on-chip regulator unless configured
for regulator off mode via REG_EN.
Crystal ground.
This pin is reserved and must be left unconnected
for proper operation.
TABLE 3-12: JTAG PIN DESCRIPTIONS
Num
Pins
1
1
1
1
Name
JTAG Test
Mux Select
JTAG Test
Clock
JTAG Test
Data Input
JTAG Test
Data Output
Symbol
TMS
TCK
TDI
TDO
Buffer
Type
VIS
VIS
VIS
VO12
Description
JTAG test mode select
JTAG test clock
JTAG data input
JTAG data output
DS00001925A-page 36
 2015 Microchip Technology Inc.