LAN9353 Datasheet, PDF (400/523 Pages) Microchip Technology – Interfaces at up to 200Mbps via Turbo MII

LAN9353
The 1588 Port x RX Pdelay_Req Ingress Time Seconds Register (1588_RX_PDREQ_SEC_x) and the 1588 Port x RX
Pdelay_Req Ingress Time NanoSeconds Register (1588_RX_PDREQ_NS_x) hold the ingress time of the Pdelay_Req
message.
The 1588 Port x RX Pdelay_Req Ingress Correction Field High Register (1588_RX_PDREQ_CF_HI_x) and the 1588
Port x RX Pdelay_Req Ingress Correction Field Low Register (1588_RX_PDREQ_CF_LOW_x) hold the correctionField
of the Pdelay_Req message.
These registers can be set by S/W prior to sending the Pdelay_Resp message.
Alternatively, these registers can be updated by the H/W when the Pdelay_Req message is received. This function is
enabled by the Auto Update (AUTO) bit in the 1588 Port x RX Pdelay_Req Ingress Time NanoSeconds Register
(1588_RX_PDREQ_NS_x) independent from the RX PTP Message Type Enable (RX_PTP_MESSAGE_EN[15:0]) bits.
As above (including all applicable notes):
• The versionPTP and domainNumber fields and alternateMasterFlag in the flagField of the PTP header are
checked, if enabled.
Note: Support for the IEEE 1588-2002 (v1) packet format is not provided.
• At the end of the frame, the frame’s FCS and the UDP checksum (for IPv4 and IPv6 formats) are verified, if
enabled.
If all tests pass, then the Pdelay_Req message information is updated.
15.2.1.4 Ingress Packet Modifications
INGRESS TIME INSERTION INTO PACKETS
As an alternate to reading the receive time stamp from registers and matching it to the correct frame received in the
Host MAC, the saved, latency adjusted, 1588 Clock value can be stored into the packet.
This function is enabled via the RX PTP Insert Timestamp Enable (RX_PTP_INSERT_TS_EN) and RX PTP Insert
Timestamp Seconds Enable (RX_PTP_INSERT_TS_SEC_EN) bits in the 1588 Port x RX Timestamp Insertion Config-
uration Register (1588_RX_TS_INSERT_CONFIG_x).
Note:
Inserting the ingress time into the packet is an additional, separately enabled, feature verses the Ingress
Time Recording described above. The capture registers are still updated as is the appropriate 1588 RX
Timestamp Interrupt (1588_RX_TS_INT[2:0]) bit and the 1588 RX Timestamp Count (1588_RX-
_TS_CNT[2:0]) field.
Following the determination of packet format and qualification of the packet as a PTP message above, the PTP header
is checked for ALL of the following.
• The messageType field of the PTP header is checked and only those messages enabled via the RX PTP Mes-
sage Type Enable (RX_PTP_MESSAGE_EN[15:0]) bits in the 1588 Port x RX Timestamp Configuration Register
(1588_RX_TIMESTAMP_CONFIG_x) will be have their ingress times inserted. Typically Sync, Delay_Req, PDe-
lay_Req and PDelay_Resp messages are enabled.
• The versionPTP field of the PTP header is checked against the RX PTP Version (RX_PTP_VERSION[3:0]) field in
the 1588 Port x RX Timestamp Configuration Register (1588_RX_TIMESTAMP_CONFIG_x). Only those mes-
sages with a matching version will be have their ingress times inserted. A setting of 0 allows any PTP version.
Note: Support for the IEEE 1588-2002 (v1) packet format is not provided.
Note: The domainNumber field and alternateMasterFlag in the flagField of the PTP header are not tested for pur-
pose of ingress time insertion.
The packet is modified as follows:
• The four bytes of nanoseconds are stored at an offset from the start of the PTP header
The offset is specified in RX PTP Insert Timestamp Offset (RX_PTP_INSERT_TS_OFFSET[5:0]) field in the 1588
Port x RX Timestamp Insertion Configuration Register (1588_RX_TS_INSERT_CONFIG_x).
The lowest two bits of the seconds are stored into the upper 2 bits of the nanoseconds.
• If also enabled, bits 3:0 of the seconds are stored into bits 3:0 of a reserved byte in the PTP header. Bits 7:4 are
set to zero.
The offset of this reserved byte is specified by the RX PTP Insert Timestamp Seconds Offset (RX_PT-
P_INSERT_TS_SEC_OFFSET[5:0]) field in the 1588 Port x RX Timestamp Insertion Configuration Register
DS00001925A-page 400
 2015 Microchip Technology Inc.